Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2002-03-12
2003-01-21
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S952000
Reexamination Certificate
active
06509251
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a resist pattern and a method of manufacturing a semiconductor device, and more particularly to a method of avoiding adverse effects caused by the deterioration in the precision of the shape of a resist pattern used in the step of implanting an impurity or the like.
2. Description of the Background Art
Hitherto, as a part of the process for manufacturing a semiconductor device, one often implants an ion seed of an impurity only into a desired region among active regions of a semiconductor substrate. At that time, a pattern of resist film (hereafter referred to as “resist pattern”) is formed to cover and hide regions where one does not wish to implant ions among the active regions and, with the resist pattern used as a mask, the ion implantation is carried out.
Referring to
FIGS. 13 and 14
, a problem in the conventional resist pattern will be described.
FIG. 14
is an arrow cross-sectional view with respect to lines XIV—XIV of FIG.
13
.
In this example, plural active regions are defined on the surface of a semiconductor substrate
5
, and the regions on the surface of semiconductor substrate
5
other than the active regions are covered with an oxide film
8
. In
FIGS. 13 and 14
, only one active region
2
is shown as the active regions; however, there are other similar active regions on semiconductor substrate
5
. A gate wiring
1
is formed in a linear configuration on this active region
2
. In this example, gate wiring
1
is formed to cross the center of active region
2
. In each of
FIGS. 13 and 14
, a resist film
3
is shown on the left side of the Figure; however, this resist film
3
is not for covering active region
2
illustrated in the Figure but is for covering a part or the whole of another adjacent active region not illustrated in the Figure. Therefore, active region
2
and resist film
3
illustrated in the Figure do not overlap with each other although they are near to each other, and there is an interval
12
between active region
2
and resist film
3
. In such a case where resist film
3
is near to active region
2
where one wishes to implant an impurity, the resist pattern is disposed to be spaced apart by a certain distance from the active region.
In order to form a resist pattern, a method of photolithography such as described below is typically adopted. First, a resist film is formed once over the entire surface of a substrate. Next, in the case of a positive resist, the portion where it is desired to remove the resist film is exposed to light, and then the portion previously exposed is dissolved and removed with a developing solution. In the case of a negative resist, only a portion where it is desired to leave the resist film is exposed to light, and then the portion previously exposed is dissolved and removed with a developing solution.
If gate wiring
1
is connected to resist film
3
as shown in
FIGS. 13 and 14
, a phenomenon occurs such that a part of the resist film remains even after the development is carried out because the resist film is not sufficiently exposed to light in the neighborhood of the site where gate wiring
1
is connected to resist film
3
, due to diffusion of light caused by the presence of gate wiring
1
at the time of exposure. This phenomenon is referred to as “trailing”. The part thus remaining on the substrate will be hereafter referred to as “trailing part”
4
. The trailing phenomenon degrades the precision of the shape of the resist pattern.
Further, even if gate wiring
1
is not connected to resist film
3
, a trailing phenomenon may also occur and a trailing part
4
a
may be formed if the interval between gate wiring
1
and resist film
3
is short as shown in FIG.
15
.
On the other hand, in accordance with the high integration and scale reduction of semiconductor devices in recent years, there may be cases in which the width of the above-mentioned interval
12
cannot be sufficiently ensured. Trailing part
4
may possibly invade into active region
2
if gate wiring
1
is present on active region
2
and gate wiring
1
is in contact with resist film
3
, as shown in
FIG. 13
, in a situation in which interval
12
is narrow to a certain extent or more. Further, in the example shown in FIG.
15
, trailing part
4
a
connected to gate wiring
1
may possibly cover a part of active region
2
where an impurity is to be implanted.
Since trailing parts
4
,
4
a
are parts where a part of resist film remains, the ion seed of the impurity is blocked by trailing parts
4
,
4
a
although trailing parts
4
,
4
a
are within active region
2
where the impurity is to be implanted. This causes insufficient implantation of the impurity. To describe this referring to the example of
FIG. 14
, though it is inherently planned to implant an impurity in a range shown by a two-dot chain line from active region
2
down to a certain depth, a loaded part
10
(part where the impurity has been implanted) does not extend to the entire range, and a non-loaded part
11
(part where the impurity has not yet been implanted) remains below trailing part
4
. Insufficient implantation into the part where the impurity is to be implanted causes adverse effects on the electrical characteristics of the semiconductor device.
Thus, an object of the present invention is to provide a method of forming a resist pattern and a method of manufacturing a semiconductor device capable of preventing deterioration in the precision of the shape of the resist pattern caused by the trailing phenomenon.
SUMMARY OF THE INVENTION
In order to achieve the aforementioned object, a method of forming a resist pattern of the present invention includes a place information inputting step of receiving a first data including information on a place where a writing is to be disposed on a substrate and a second data including information on a place where a resist pattern for blocking implantation of an impurity into an active region on the substrate is to be disposed, and a resist pattern determining step of determining the resist pattern by retreating a contour of the resist pattern at a site where a part of the place where the wiring is to be disposed, which part is located on the active region, as defined by the first data and the place where the resist pattern is to be disposed as defined by the second data are near to each other by a predetermined distance or less so that the contour of the resist pattern may be located away from the part to correspond to a shape of the part. By adopting this method, one can avoid a situation in which the trailing part covers the active region even if the trailing phenomenon occurs at the site where the part of the place where the wiring is to be disposed, which part is located on the active region, and the place where the resist pattern is to be disposed are near to each other.
In order to achieve the aforementioned object, a method of manufacturing a semiconductor device according to one aspect of the present invention includes a place information inputting step of receiving a first data including information on a place where a gate wiring is to be disposed on a substrate and a second data including information on a place where a resist pattern for blocking implantation of an impurity into an active region on the substrate is to be disposed, and a resist pattern determining step of determining the resist pattern by retreating a contour of the resist pattern at a site where a part of the place where the gate wiring is to be disposed, which part is located on the active region, as defined by the first data and the place where the resist pattern is to be disposed as defined by the second data are near to each other by a predetermined distance or less so that the contour of the resist pattern may be located away from the part to correspond to a shape of the part. By adopting this method, one can avoid a situation in which the trailing part covers the active region even if the trailing phenomenon occurs at the si
Hattori Sachiko
Saito Takayuki
Chaudhuri Olik
Smoot Stephen W.
LandOfFree
Method of forming a resist pattern for blocking implantation... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming a resist pattern for blocking implantation..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a resist pattern for blocking implantation... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3035484