Method of forming a multi-layer semiconductor structure...

Details Method of forming a multi-layer semiconductor structure... Method of forming a multi-layer semiconductor structure...

2006-06-20

2006-06-20

Kang, Donghee (Department: 2811)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S612000, C438S613000, C438S615000

Reexamination Certificate

active

07064055

ABSTRACT:
A method of forming a multi-layer semiconductor structure includes providing a first layer of a patterned copper bond film having a first predetermined thickness onto a first surface of a first semiconductor. The method further includes providing a second layer of a patterned copper bond film having a second predetermined thickness onto a first surface of a second semiconductor. The first and second semiconductor structures can be aligned, such that the first and second patterned copper bond films are disposed in proximity. A virtually seamless bond can be formed between the first and second patterned copper bond films to provide the first and second semiconductors as the multi-layer semiconductor structure.

REFERENCES:
patent: 4313126 (1982-01-01), Krumm et al.
patent: 4402761 (1983-09-01), Feist
patent: 4456888 (1984-06-01), Ayasli
patent: 4599704 (1986-07-01), Mazin
patent: 4939568 (1990-07-01), Kato et al.
patent: 4986861 (1991-01-01), Nishida et al.
patent: 5156997 (1992-10-01), Kumar et al.
patent: 5206186 (1993-04-01), Neugebauer et al.
patent: 5236118 (1993-08-01), Bower et al.
patent: 5270261 (1993-12-01), Bertin et al.
patent: 5370301 (1994-12-01), Belcher et al.
patent: 5391257 (1995-02-01), Sullivan et al.
patent: 5445994 (1995-08-01), Gilton
patent: 5504376 (1996-04-01), Sugahara et al.
patent: 5523628 (1996-06-01), Williams et al.
patent: 5563084 (1996-10-01), Ramm et al.
patent: 5669545 (1997-09-01), Pham et al.
patent: 5706578 (1998-01-01), Hubner
patent: 5767009 (1998-06-01), Yoshida et al.
patent: 5821138 (1998-10-01), Yamazaki et al.
patent: 5825080 (1998-10-01), Imaoka et al.
patent: 5902118 (1999-05-01), Hubner
patent: 5904562 (1999-05-01), Nulman
patent: 5923087 (1999-07-01), Suzuki et al.
patent: 5940683 (1999-08-01), Holm et al.
patent: 5985693 (1999-11-01), Leedy
patent: 5998808 (1999-12-01), Matsushita
patent: 6027958 (2000-02-01), Vu et al.
patent: 6441478 (2002-08-01), Park
patent: 6465892 (2002-10-01), Suga
patent: 6525415 (2003-02-01), Koyanagi et al.
patent: 6600173 (2003-07-01), Tiwari
patent: 6717244 (2004-04-01), Hikita et al.
patent: 2002/0050635 (2002-05-01), Ogura et al.
patent: 2002/0074670 (2002-06-01), Suga
patent: 2002/0109236 (2002-08-01), Kim et al.
patent: 2002/0135062 (2002-09-01), Mastromatteo et al.
patent: 2002/0135075 (2002-09-01), Leedy
patent: 2004/0124538 (2004-07-01), Reif et al.
patent: 2004/0126994 (2004-07-01), Reif et al.
patent: 2004/0219765 (2004-11-01), Reif et al.
patent: 100 47 963 A 1 (2001-03-01), None
patent: 1 041 624 (2000-10-01), None
patent: 1 151 962 (2001-07-01), None
patent: 1 432 032 (2004-06-01), None
patent: 2 645 681 (1990-10-01), None
patent: WO 02/09182 (2002-01-01), None
A.Fan et a., “Copper Wafer Bonding”, Electrochemical and Solid-State Letters, 2(10) 534-536 (1999).
Mark Lapedus, Tezzaron Devises Multi-Wafer Slack for 3-D Chips, Jun. 30, 2003, Naperville, Illinois, p. 1.
Chris Gaither, Intel Set To Unveil Advanced Communications Chip, The Boston Globe, Oct. 15, 2002, pp. 1-3, Boston, Massachusetts.
Peter Clarke, IEDM Late Paper. IBM Shows How to Stack for 3D Circuitry, Silicon Strategies.Com, Nov. 28, 2002, pp. 1-2, London.
TRU-SI Technologies, Through-Silicon Vias, Tru-Si Technologies Home Page, Apr. 7, 2003, p. 1, Sunnyvale, California.
Mark Lapedus, Tezzaron Devises Multi-Wafer Stack for 3-D Chips, Semiconductors EE Times, Jun. 30, 2003, pp. 1-3, Naperville, Illinois.
Osamu Tabata, Anisotropic Etching of Silicon in TMAH Solutions, Toyota Central Research and Development Laboratories, Inc., Feb. 21, 1992, pp. 51-57, Japan.
Philip M. Sailer, Creating 3D Circuits Using Transferred Films, Circuits & Devices, Nov. 1997, pp. 27-30.
Takuji Matsumoto, New Three-Dimensional Wafer Bonding Technology Using the Adhesive Injection Method, Mar., 1998, pp. 1217-1221. Jpn., J. Appl. Phys. vol. 37 (1998).
A. Fan, Copper Wafer Bonding, Electrochemical and Solid-State Letters, 1999, pp. 534-536, Cambridge, Massachusetts.
Arifur Rahman, Wire-Length Distribution of Three-Dimensional Integrated Circuits, 1999, pp. 233-235.
Victor W.C. Chan, Three Dimensional CMOS Integrated Circuits on Large Grain Polysilicon Films, EEE, Hong Kong University of Science and Technology, 2000, pp. 00-161-00-164 Hong Kong.
K.W. Lee, Three-Dimensional Shared Memory Fabricated Using Wafer Stacking Technology, Dept. of Machine Intelligence and Systems Engineering. 2000, pp. 00-165-00-168, Hong Kong.
Kuan-Neng Chen, Microstructure Examination of Copper Wafer Bonding, Microsystem Technology Laoratories, Dec. 20, 2000, pp. 331-335, Cambridge, Massachusetts.
Y. Hayashi, Fabrication of Three Dimensional IC Using “Cumulatively Bonded IC” (CUBIC) Technology Symposium on VLSI Technology, 1990, pp. 95-96.
PCT/US/03/41514 International Search Report Jun. 17, 2004.
PCT/US 03/41407. International Search Report, Sep. 15, 2004.

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