Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2002-01-22
2003-12-16
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S527000, C438S706000
Reexamination Certificate
active
06664172
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a method of forming a metal-oxide-semiconductor (MOS) transistor, and more particularly, to a method of improving the threshold voltage stability of a MOS transistor.
2. Description of the Prior Art
In today's electronics industry, semiconductors are the most extensively used devices. Previous developments such as the PN diode and the bipolar junction transistor (BJT) showed how electronic devices could make use of the unique characteristics of semiconductor materials. Because semiconductors are solid-state devices, it has been possible to shrink them to incredibly small sizes, and the drive towards miniaturization has led the semiconductor industry to progress rapidly in the past few years. Most recently, transistors known as metal-oxide semiconductor (MOS) transistors have been created that consume less power and can be highly integrated. These tiny transistors have gradually replaced the BJT, and are widely used in various electronic devices and logic circuits.
The progress of the science and technology has led to continual improvements in the performance of electronic devices and logic circuits. These improvements have fueled the increased demand for MOS transistors. In a MOS transistor, one of the most basic and critical requirements for proper operation is a stable threshold voltage. If the threshold voltage of a MOS transistor is unstable or out of spec, the turn-on and turn-off of the MOS transistor become abnormal and further affect the accuracy of the operation of integrated circuit. Not only does one need to satisfy the demand of a stable threshold voltage, but also demands of other electrical characteristics, such as turn-on speed, power dissipation, and leakage current.
Please refer to FIG.
1
through FIG.
4
. FIG.
1
through
FIG. 4
are schematic diagrams showing the formation of a MOS transistor
38
according to the prior art method. As shown in
FIG. 1
, a prior art MOS transistor
38
is made on a semiconductor wafer
10
. The semiconductor wafer
10
comprises a semiconductor substrate
11
, a P-well
12
on the semiconductor substrate
11
, and a plurality of isolators
14
positioned on the surface of the P-well
12
. The isolator
14
is usually a field oxide layer formed by a oxidation (LOCOS) or a shallow trench isolation (STI), and is used to define an active area
15
for each MOS transistor.
As shown in
FIG. 2
, a thermal oxidation process and a low pressure chemical vapor deposition (LPCVD) process are performed to homogeneously and sequentially form a silicon dioxide layer (SiO
2
layer, not shown) and a doped polysilcion layer (not shown) on the surface of the semiconductor wafer
10
. Then a first photoresist layer
16
is coated on the surface of the semiconductor wafer
10
. This is followed by a photolithography process to define the pattern of each gate
18
in the photoresist layer
16
. Thereafter a dry etching process is performed to form the gate
18
, which comprises a gate oxide layer
22
and a gate conductive layer
24
, on the surface of the semiconductor wafer
10
. Finally, the photoresist layer
16
is removed.
As shown in
FIG. 3
, the next step is to perform an ion implantation process to form a lightly doped drain (LDD)
26
at either side of the transistor gate
18
. A chemical vapor deposition (CVD) process is then performed to deposit a silicon nitride layer
28
on the surface of the semiconductor wafer
10
, and an anisotropic dry etching process is performed to remove the silicon nitride layer
28
down to the surface of the p-well
12
so as to form a spacer
32
on each lateral side of the gate
18
. The CVD process, being a low thermal budget process, is characterized as a low deposition temperature process. It is usually performed in a single wafer type chamber for plasma enhanced chemical vapor deposition (PECVD) processes at a reaction temperature less than 450° C. Or it is performed in a single wafer type chamber or a batch type chamber for chemical vapor deposition (CVD) process at a reaction temperature ranging from 600 to 700° C.
Thus, avoid an unexpected drive-in of the dopants in the lightly doped drain
26
due to high temperature, which would further alter the profile of the lightly doped drain
26
and affect the operational speed and power dissipation of the MOS transistor
38
. Since the silicon nitride layer
28
is characterized as a high tensile stress layer, cracks in this layer are readily produced. The tensile stress of the silicon nitride layer can be lowered by adjusting the radio frequency power in the PECVD process to control the bombardment of ions to deposited film. Or, a silicon dioxide layer, being a linear oxide layer having a lower tensile stress, can be deposited or grown before depositing the silicon nitride layer, and can be used as a buffer layer for improving the adhesion between the silicon nitride layer and the silicon surface. It is worth noticing that the growth reaction, which is a rapid thermal processing (RTP), having a high process temperature and a short reaction time, is characterized as a low thermal budget process. Therefore, there will be no impact on the formed lightly doped drain.
As shown in
FIG. 4
, another ion implantation process is thereafter performed by utilizing the gate
18
and the spacer
32
as a hard mask to implant N-type dopants into the P-well
12
at either side of the spacer
32
so as to form a source
34
and drain
36
of the MOS transistor. The semiconductor wafer
10
is then put into a furnace and a drive-in process is performed to diffuse the dopants to expected profile and complete the MOS transistor
38
.
However, there is a problem with the prior art method for forming the MOS transistor. Please refer to
FIG. 5
,
FIG. 5
is a schematic diagram of interface trapped charges
52
resulting from the low thermal budget chemical vapor deposition process for forming the spacer
32
according to the prior art. The silicon nitride deposited by the PECVD process contains an amount of hydrogen (H) from 7~30%, depending on the process parameters. The hydrogen content comes from Si—H bonds and N—H bonds, which form when a precursor with a low dissociation temperature loses hydrogen atoms to unsaturated silicon (S) and nitrogen (N) atoms during the low thermal budget chemical vapor deposition process. The diffusion velocity of hydrogen atoms is rapid due to their small size. As a result, the hydrogen atoms near the gate are readily diffused into the Si—SiO
2
interface
50
. Owing to the discontinuous property of the Si—SiO
2
interface, H atoms are trapped into the Si—SiO
2
interface and become interface-trapped charges (Q
it
)
52
, as shown in FIG.
5
. In addition, Q
it
are dependent on the chemical composition of the Si—SiO
2
interface. The interface trap density (i.e., number of interface traps per unit area) can be reduced by both using adequate annealing process and selecting wafers with low traps, such as the <100> oriented silicon wafer. However, interface traps cannot be eliminated completely.
For any MOS transistor, the threshold voltage (V
t
) is the smallest gate voltage required for the onset of strong inversion on the surface of a semiconductor. This is given by
V
t
=V
FB
+Q
B
/C
OX
+2&phgr;
B
where V
FB
denotes the flat band voltage, Q
B
denotes the charge density contained within the surface depletion region at the onset of strong inversion, C
OX
denotes the capacitance of the oxide layer, and &phgr;
B
denotes the bulk potential of the semiconductor. Due to the existence of the interface-trapped charges, the magnitude of the flat band voltage is changed, and as a result, the magnitude of the threshold voltage is changed. The above description uses the example of an NMOS transistor made on a P-type substrate with positive interface-trapped charges. However, it is also possible to have a PMOS transistor made on an N-type substrate. The interface-trapped charges can be negative or positive for both PMOS and NMOS tran
Chen Chung-Yi
Lee Tong-Hsin
Elms Richard
Hsu Winston
Smith Brad
United Microelectronics Corp.
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