Method of forming a MIS capacitor

Details Method of forming a MIS capacitor Method of forming a MIS capacitor

2000-08-23

2003-04-15

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S381000, C438S387000, C438S240000, C438S513000, C438S680000, C438S769000, C257S296000, C257S303000, C257S306000, C257S310000, C257S639000, C257S640000

Reexamination Certificate

active

06548368

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of semiconductor manufacturing. More specifically, the present invention relates to a method of integrating tantalum pentaoxide into an MIS stack capacitor using low thermal budget.
2. Description of the Related Art
Integrated circuits are made up of literally millions of active and passive devices such as transistors, capacitors and resistors. A dynamic random access memory (DRAM) capacitor generally includes a stack capacitor and a trench capacitor. The stack capacitor includes a fin structure, a cylinder structure, and a box structure. The cylinder structure is generally used taking the capacitance into consideration.
In order to provide more computational power and/or more storage capability, DRAM capacitors are scaled down and made more and more compact with shrinking device geometry (see FIG.
1
). A more compact DRAM capacitor requires higher capacitance. For example, memory structures with bit density of 4G or higher have capacitor area of 0.25×0.25 &mgr;m
2
or smaller and require capacitance/area storage elements higher than 300 fF/&mgr;m
2
. For high capacitance, it is suggested that a contact area of a storage node electrode and a plate electrode be made large in a limited cell area and that the dielectric film be formed of a material having a high dielectric ratio (see FIG.
2
).
High dielectric constant films are generally ceramic films (i.e., metal-oxides) such as tantalum pentaoxide. Tantalum pentaoxide (Ta
2
O
5
) is a desired capacitor dielectric material due to its high dielectric constant of about 25. In contrast, other commonly utilized dielectric materials have much lower dielectric constants. For instance, silicon nitride has a dielectric constant of about 8 and silicon dioxide has a dielectric constant of about 4. Due to the high dielectric constant of Ta
2
O
5
, a thinner layer of Ta
2
O
5
can be utilized in capacitor constructions to achieve the same capacitance as thicker layers of other materials.
Semiconductive capacitors comprise a first conductive plate and a second conductive plate, with a dielectric layer formed between the plates. Commonly, the conductive plates comprise doped polysilicon, with one or both of the plates comprising a rugged form of polysilicon, such as, for example, hemispherical grain polysilicon (HSG). When dielectric films are deposited, they tend to have vacancies at the anionic (oxygen) sites in the lattice. Presently these vacancies are filled by annealing the film in an oxygen containing gas. However, this annealing causes oxidation of the underlying polysilicon electrode, which causes the formation of a silicon dioxide film in series with the high dielectric constant film which in turn reduces the effective dielectric constant of the combined film.
When utilizing Ta
2
O
5
as the dielectric layer in DRAM capacitors, the chemical vapor deposition (CVD) processes by which Ta
2
O
5
is formed adversely complicate its incorporation into semiconductive capacitors. For instance, Ta
2
O
5
is not typically deposited onto a first polysilicon plate, nor is a second polysilicon plate typically directly deposited onto Ta
2
O
5
. The underlying and overlying polysilicon layers are affected adversely by the Ta
2
O
5
-forming CVD processes unless such polysilicon layers are first protected with barrier layers. Presently, Ta
2
O
5
is typically formed by a CVD process in which Ta(OC
2
H
5
)
5
(TAETO) and oxygen are combined. Unless a polysilicon plate is protected by a barrier layer before such CVD deposition over the polysilicon, the oxygen of the CVD process will react with the polysilicon to disadvantageously form a layer of silicon dioxide over the polysilicon.
Currently available methods for protecting the polysilicon include provision of a silicon nitride layer over the polysilicon prior to deposition of Ta
2
O
5
. The silicon nitride layer is typically 10 to 25 angstroms thick. However, Ta
2
O
5
integration as deposited (see
FIG. 3
) is deficient in oxygen and forms a very leaky film as shown in FIG.
4
. That is, it has a large leakage current. Since oxidation anneal of the film is essential to make Ta
2
O
5
a useful dielectric material for highly integrated device, proper thermal oxidation annealing condition is important for Ta
2
O
5
integration.
FIG. 5
shows that oxidation in a stronger oxidizing environment improves J−V characteristics, but the capacitance goes down significantly (i.e., T
ox
increases). Therefore, proper oxidation is needed to make Ta
2
O
5
a useful dielectric, which provides high capacitance and low leakage current at the same time.
High temperature oxidation is commonly used, wherein the oxidization step employed comprises a rapid thermal oxidation (RTO) process which is typically carried out at a temperature of from about 700 to about 1150° C., or comprises rapid thermal annealing (RTA) using the N
2
O gas, which is carried out at a temperature of 800° C. Ta
2
O
5
as integrated provides good electrical performance (i.e., low leakage current); however, the capacitance might not be efficiently high.
Therefore, the prior art is deficient in the lack of effective means of integrating Ta
2
O
5
into an MIS capacitor, particularly to provide both high capacitance and low leakage current. The present invention fulfills this long-standing need and desire in the art.
SUMMARY OF THE INVENTION
In one embodiment, there is provided a method of forming an MIS capacitor, comprising the step of forming a silicon oxynitride layer at the interface of a silicon surface of a substrate and a dielectric film. This method could further comprise a step of annealing the dielectric film.
In another embodiment, there is provided a method of integrating Ta
2
O
5
into an MIS stack capacitor for a semiconductor device, comprising the step of forming a thin barrier layer at the Si/TaO interface.
Various tantalum-containing precursors are used for depositing tantalum pentaoxide. The present data shows that proper sequencing of the deposition process leads to similar results with either TAETO or TAT-DMAE. Therefore, a method is hereby provided to form an MIS stack capacitor, comprising the steps of: forming a silicon nitride film on a silicon surface of a substrate; treating the silicon nitride film with rapid thermal oxidation to form a silicon oxynitride film, wherein the silicon nitride film is eliminated; and depositing tantalum pentaoxide above the silicon oxynitride film with a Ta-containing precursor.
Other and further aspects, features, and advantages of the present invention will be apparent from the following description of the embodiments of the invention given for the purpose of disclosure.


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Fazan et al. “Ultrathin oxide
itride dielectrics for rugged stacked dram capacitors” IEEE Electron device letters vol. 13 No. 2 Feb. 1992 pp. 86-88.*
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