Method of forming a metal silicide gate in a standard MOS...

Details Method of forming a metal silicide gate in a standard MOS... Method of forming a metal silicide gate in a standard MOS...

2003-03-18

2004-11-23

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S005000, C438S683000, C438S592000, C438S655000, C438S656000, C438S660000, C438S666000, C438S668000, C438S685000, C438S686000

Reexamination Certificate

active

06821887

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the manufacture of semiconductor structures, and, more particularly, to the fabrication of MOS transistor devices having gate electrodes with a reduced gate length, especially in the sub 0.25 &mgr;m range.
2. Description of the Related Art
In sophisticated integrated circuits, the feature sizes of circuit elements, such as CMOS (complementary metal oxide semiconductor) transistors, are presently scaled into the deep sub-micron regime for higher integration density and improved device performance. The scaling of critical dimensions, such as the gate length of a MOS transistor, may, however, degrade other related device characteristics so that the advantages obtained by decreasing the feature sizes may partially be offset. For example, the reduction of the gate length, and thus the channel length, of a MOS transistor requires the corresponding scaling of the gate insulation layer that separates the gate electrode from the channel region to provide the required drive current capability for reduced supply voltages that are required to maintain the strength of the electrical field within an acceptable range. Thinning the gate insulation layer, so as to ensure a sufficient capacitive coupling of the gate electrode to the underlying channel region, may allow for compensation of a decreased gate voltage for MOS transistors having a gate length in the range of 0.5 &mgr;m and less. However, severe problems may arise for MOS transistors in the deep sub-micron regime, for example, having a gate length in the range of 0.1 &mgr;m and less, since a plurality of problems render it difficult to provide the desired drive current capability.
One issue of MOS transistors having a gate length in the deep sub-micron range requiring a thickness of the gate insulation layer, usually formed of silicon dioxide, in the range of 2-4 nm resides is the fact that a depletion layer forms within the polysilicon gate electrode. This depletion layer increases the effective thickness of the gate insulation layer and, therefore, reduces the capacitive coupling of the gate electrode to the underlying channel region. Although the formation of the depletion layer may be substantially eliminated by heavily doping the polysilicon gate electrode, it turns out, however, that, in particular for P-channel MOS transistors requiring doping with boron, dopants readily penetrate the gate insulation layer and may also enter the channel region. The former effect may significantly degrade the gate oxide quality of the gate insulation layer, thereby reducing device reliability, whereas the latter effect may lead to a significant shift of the threshold voltage of the transistor device due to the additional dopants introduced into the channel region.
In addition to the formation of a gate depletion layer, especially in P-channel MOS transistors, the polysilicon gate electrode, with reduced gate length, suffers from a reduced conductivity due to the reduced cross-sectional dimension of the gate electrode.
In view of the above problems, great efforts are presently being made to replace the polysilicon with a highly conductive material that allows the elimination, or at least the substantial reduction, of the above identified problems. For instance, metal gate MOS devices have been suggested, and a significantly reduced sheet resistance is obtained, wherein additionally the effect of gate depletion may be substantially eliminated. However, since the vast majority of metals suited for a gate material in MOS applications cannot withstand high temperature thermal process sequences as required in the MOS manufacturing process, such as the rapid thermal annealing for activating implanted dopants and for curing implantation induced lattice damage, complex alternative integration process sequences are required to integrate metal gates into MOS integrated circuits.
In view of the above problems, there exists a need for an improved MOS transistor element that may be manufactured in a compatible fashion with standard MOS manufacturing.
SUMMARY OF THE INVENTION
Generally, according to the present invention, a MOS transistor element may be fabricated using well-established MOS process sequences, wherein, contrary to the conventional approach, a polysilicon layer acting as the gate electrode is substantially completely transformed into a metal silicide so that the sheet resistance and the formation of a gate depletion layer is significantly reduced. By appropriately adjusting the thickness of the polysilicon layer from which the gate electrode is to be patterned, and correspondingly controlling process parameters of a subsequent suicide process, standard process recipes may be effectively employed without compromising integrity of the source and drain junctions.
According to one illustrative embodiment of the present invention, a method of forming a gate electrode of a MOS transistor comprises determining a height of a metal silicide layer of a specified metal formed in a crystalline silicon layer under predefined process conditions. Then, a design height is selected for forming the metal silicide layer in the gate electrode to be formed under the predefined process conditions. Next, a thickness of a metal silicide layer of the specified metal is determined that is formed in a polysilicon layer under the predefined process conditions and the height of the metal silicide layer in the polysilicon layer is selected as a target deposition thickness for forming the gate electrode. Moreover, a substrate is provided having formed thereon a doped silicon region and a gate insulation layer is formed on the doped semiconductor region. Thereafter, a polysilicon gate layer with a thickness corresponding to the target deposition thickness is deposited and patterned to form the gate electrode. A metal layer comprising the specified metal is deposited over the gate electrode and a heat treatment is performed under the specified process conditions to convert polysilicon in the gate electrode into a metal silicide.
According to one illustrative embodiment of the present invention, a method of forming a gate electrode of a MOS transistor comprises determining, as a first target deposition thickness, a thickness of a specified metal layer that is consumed in forming a metal silicide layer of a predefined design height in a crystalline silicon region. The method further includes determining, as a second target deposition thickness, a height of a metal silicide layer of the specified metal that forms in a polysilicon region when the specified metal layer having the first target deposition thickness is substantially completely consumed. The method further comprises providing a substrate having formed thereon a doped semiconductor region and forming a gate insulation layer on the doped semiconductor region. Next, a polysilicon gate layer is deposited on the gate insulation layer with a thickness corresponding to the second target deposition thickness and is patterned to form the gate electrode. Thereafter, a metal layer comprising the specified metal is deposited with a thickness corresponding to the first target deposition thickness. Finally, a heat treatment is performed with the substrate to substantially completely convert the metal layer into metal silicide.
In a further embodiment of the present invention, a MOS transistor comprises a substrate including a well region. A drain region and a source region are formed in the well region and a gate insulation layer is formed adjacent to the well region. Moreover, a gate electrode is formed on the gate insulation layer, wherein at least 90% of the gate electrode is comprised of a metal suicide.


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