Method of forming a low stress polycide conductors on a semicond

Details Method of forming a low stress polycide conductors on a semicond Method of forming a low stress polycide conductors on a semicond

1995-10-31

1998-12-15

Bowers, Charles

Semiconductor device manufacturing: process

Formation of semiconductive active region on any substrate

Polycrystalline semiconductor

438491, 438253, 438418, 438417, 438592, 438657, 438658, 438659, 438396, H01L 2170

Patent

active

058496297

ABSTRACT:
A method of forming low resistivity conductive lines on a semiconductor substrate is disclosed. In practicing the method a multichamber tool is used to advantage by forming a first doped polysilicon layer on the surface of a substrate, forming a second undoped layer on the doped layer, while maintaining the work piece under a vacuum environment, moving the substrate to a second chamber and thereafter forming a silicide containing layer on the undoped polysilicon layer. Various techniques may be used to deposit either the polysilicon or the silicide layer such as sputtering may also be used. Practice of the method eliminates separation of silicide from polysilicon and increases product yield.

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"Integrated In-Situ Doped Polysilicon/Tungsten Silicide Gate Conductor" IBM Technical Disclosure, vol. 38, No. 06, Jun. 1995.

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