Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-11-13
2004-07-06
Kielin, Erik J. (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S688000
Reexamination Certificate
active
06759324
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor integrated device design and fabrication and, more particularly, to methods of manufacturing intermetal contacts for high-density dynamic random access memory arrays.
2. Description of the Related Art
In large scale semiconductor integrated circuit technology, the trend of increasing circuit density makes vertical circuit integration one of the critical aspects of current manufacturing processes. This is of particular relevance to the manufacture of multi-level interconnect structures (i.e., wiring). Large scale integrated semiconductor circuits can have multiple layers of electrically conductive films to interconnect various active device regions which are located on a semiconductor substrate. In the semiconductor industry, these conductive films are often referred to as lines or runners.
Aluminum has been the most widely used conductive material in the manufacture of semiconductor integrated circuits. The main reason for the pervasiveness of aluminum is its low resistivity (2.7 &mgr;&OHgr;-cm) and its good adhesion to SiO
2
and silicon. Additionally, the use of aluminum thin-films in multilevel metal systems is a well-understood process.
Modem devices generally have at least three layers of conductive lines in their vertical circuitry. Typically, the first layer is provided for local interconnections while the upper layers are generally provided for global interconnections (i.e., across the entire chip). The conductive lines at different elevations are normally separated from one another by an insulating interlevel dielectric, such as silicon dioxide. Interconnections between these conductive lines can be provided by metal-filled vias. Conventionally, vias are opened through the interlevel dielectric so as to expose a contact region on the underlying conductor. An upper conductive layer is connected to the lower conductive layer at this contact region.
FIG. 1A
illustrates a typical prior art multilevel structure using two layers of conductive lines. This multilevel structure comprises a lower aluminum layer
106
which is deposited on a first interlevel dielectric
102
and within a contact opening
104
. The lower aluminum layer fills the contact opening
104
and contacts an active area
103
on a substrate
101
. A second interlevel dielectric
108
is typically used to isolate the lower aluminum layer
106
from an upper conductor layer
112
, such as an aluminum or tungsten layer. The upper conductor layer
112
covers the second interlevel dielectric
108
and fills the via opening
107
. The upper conductor layer
112
contacts the lower aluminum layer at a contact location
109
in the via opening
107
. Finally, a top insulating layer
114
is deposited on the upper conductor layer
112
.
As illustrated in
FIG. 1A
, the upper conductor layer
112
establishes electrical contact with the lower aluminum layer
106
at the contact location
109
. In a semiconductor integrated circuit, the electrical resistivity of such contact locations is significant enough to influence overall speed and reliability of the semiconductor device. Ideally, the electrical resistivity of the via contact must be as low as possible. However, conventional contacts display an unacceptable level of high resistivity due to an aluminum oxide layer primarily forming on the lower aluminum layer, specifically at the contact location. The aluminum oxide forms spontaneously when the aluminum material is exposed to an oxidizing atmosphere. Although the thickness of the aluminum oxide layer is only 50 Å to 60 Å, the aluminum oxide produces an insulation barrier between the upper conductor and the lower aluminum layer, and greatly degrades the electrical contact between them, even in this thickness regime.
The aluminum layer will generally be exposed to an oxidizing atmosphere at some point in conventional fabrication process flows, causing an oxide layer to form on the aluminum. For example, referring to
FIG. 1
, an oxide layer (not shown) on the lower aluminum layer
106
may primarily form after the deposition of the lower aluminum layer
106
when the aluminum layer is exposed to air. Similarly, an oxide layer may form during deposition of the interlevel dielectric
108
when the surface of the aluminum layer is exposed to oxidizing gases during such deposition. Additionally, oxidation of the aluminum can occur during etch processes used for opening vias in interlevel dielectrics. In such processes, the via openings
107
can be etched using a variety of etching techniques such as wet etching, plasma etching and reactive ion etching. Once the interlevel dielectric
108
is removed from the via opening
107
, the contact region
109
is exposed to the reactive etchant solutions or gases resulting in oxidation of the location
109
.
One manner of reducing resistivity has been to deposit a layer of titanium before the deposition of the upper conductor layer. As illustrated in
FIG. 1B
, a layer of titanium
110
is deposited on a patterned and etched second interlevel dielectric (ILD)
108
, prior to filling the via
107
with a second conductive layer
112
. Conventionally, the titanium layer has been deposited using a sputter deposition technique to a thickness of greater than about 500 Å over the ILD
108
for contact dimensions on the order of about 1 &mgr;m. More recently, the titanium layer has been deposited to a thickness of about 200 Å for similar contact dimensions. In accordance with conventional scaling techniques, reduction of via opening dimensions and/or increasing aspect ratios would be compensated by increasing the amount of deposited titanium, such that adequate coverage of the via bottom is maintained.
As increasing circuit densities result in narrower and deeper via openings, adequate electrical connection through these deep and narrow openings becomes ever more important to the speed and reliability of the circuit. As the contact region gets smaller, the electrical resistivity levels provided by prior art processes become less satisfactory. Thus, there is a need for processes and structures for reducing resistivities in integrated circuit contacts.
SUMMARY OF THE INVENTION
The aforementioned needs are satisfied by the processes and structures disclosed herein, by which the electrical resistivity of an interlevel contact can be optimized.
In accordance with one aspect of the invention, a process is provided for forming low resistance contacts between conducting lines in an integrated circuit. The process involves forming a first metallic layer over a semiconductor substrate, and an insulating layer over a first surface of the metallic layer. A patterned mask is formed over the insulating layer, with an opening of an opening of less than about 0.75 &mgr;m. A contact via is then etched through the opening to expose a contact region of the first surface. The mask is removed, and a titanium layer deposited over the insulating layer and into the via. The titanium layer is deposited to a thickness between about 300 Å and 400 Å over the insulating layer.
In accordance with another aspect of the present invention, a method is provided for forming an integrated circuit with a low resistivity intermetal contact through an insulating layer. The method includes forming a first conductive layer, which includes aluminum, over a semiconductor substrate, and forming an insulating layer on an upper surface of the first conductive layer. A contact via of a selected size and shape is etched in the insulating layer to expose a contact region of the upper surface of the first conductive layer. Aluminum oxide forms on the first conductive layer, at least within the contact region. An amount of titanium required for 60 Å to 300 Å to reach the bottom of such a via is then determined, and this determined amount is deposited over the insulating layer. The titanium which reaches the via bottom is then reacted with the underlying aluminum, forming a
Rhodes Howard E.
Tang Sanh
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