Method of forming a low-K dual damascene interconnect structure

Details Method of forming a low-K dual damascene interconnect structure Method of forming a low-K dual damascene interconnect structure

2006-11-07

2006-11-07

Chen, Kin-Chan (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S700000, C438S738000

Reexamination Certificate

active

07132369

ABSTRACT:
A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.

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