Method of forming a local interconnect contact opening

Details Method of forming a local interconnect contact opening Method of forming a local interconnect contact opening

2000-10-10

2002-06-25

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S638000, C438S672000, C438S675000, C438S706000, C438S736000

Reexamination Certificate

active

06410422

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89119722, filed Sep. 25, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor fabrication method. More particularly, the present invention relates to a method of fabricating a local interconnect contact opening.
2. Description of the Related Art
After the metal-oxide semiconductor (MOS) transistors of the integrated circuit are formed, contact plugs and metal lines are used to provide connection between MOS transistors, or between source/drain regions. Typical contact plugs and metal lines are formed by first forming a MOS transistor and then forming a dielectric layer over the substrate. Thereafter, a contact opening is formed in the dielectric layer by a photolithographic and etching process. A metal layer is formed over the dielectric layer to fill the contact opening. A photolithographic and etching process is performed to pattern the metal layer. A fabrication process of forming a contact plug and a metal line is thus completed.
When design rules becomes more complex, because of the limitation of the photolithographic technique, it is difficult to simultaneously form a dense distribution of contact openings in a dielectric layer. In order to overcome this difficulty, the current method uses one single contact instead of using the contact nodes having an equal electrical potential. This method is described as follows. A dielectric layer is formed over the substrate. A photolithographic and etching process is performed. A local interconnect contact opening exposing both gate and the source/drain region of the gate is formed in the dielectric layer. In addition, a share contact opening, which exposes both the gate and a source/drain region on one side of the gate, is formed in the dielectric layer, simultaneously. Thereafter, a conductive material is filled in the local interconnect contact opening and the share contact opening. A local interconnect contact and a share contact are thus formed.
The above-described method increases the fabrication window of the photolithographic process. However, the opening size difference among the local interconnection contact opening, the share contact opening, and the contact openings that only exposes the source/drain region are great. This, in turn, induces microloading effect. In addition, because the dielectric layer varies in thickness, the depths of contact openings are different. Thus, the selection of the etchant of the above method is very important. Otherwise, the micro-loading effect arising from non-uniform etching and over-etching caused by different depths of the openings will easily occur.
SUMMARY OF THE INVENTION
The invention provides a method of forming a local interconnect contact opening. A liner layer is formed on a substrate having a gate structure, a first source/drain region, and a second source/drain region formed thereon. A planarized dielectric layer is formed over the liner layer. A photoresist layer, which defines the location of the local interconnect contact opening, is formed over the dielectric layer. A one-step etching process is performed using a C
5
F
8
/CO/O
2
/Ar etching gas and the liner layer as an etching stop. The dielectric layer exposed by the opening of the photoresist layer is removed to expose the liner layer. The liner layer and the photoresist layer are removed.
The present invention further provides a method of forming contact openings having different depths and different opening sizes. A substrate having a gate structure and source/drain region formed thereon is provided. A liner layer is formed over the substrate to cover the gate structure and the source/drain regions. A planarized dielectric layer. A photoresist layer is formed over the dielectric layer to expose locations of contact openings. A one-step etching process is performed using a C
5
F
8
/CO/O
2
/Ar etching gas and using the liner layer as an etching stop to etch the dielectric layer exposed by the photoresist layer. After the etching process is performed, a local interconnect contact opening, a share contact opening, and a borderless opening are formed to expose the liner layer. Both the local interconnect opening and the share contact opening and the share contact opening have a first depth and a second depth. An opening size of the local interconnect opening is larger than an opening size of the share contact opening. An opening size of the share contact opening is larger that an opening size of the borderless opening. Portions of the liner layer exposed by the local interconnect opening, the share contact opening, the borderless contact opening are removed to expose the gate structure and the source/drain regions. The photoresist layer is removed.
In the C
5
F
8
/CO/O
2
/Ar etching gas, a C
5
F
8
gas has a flow rate of about 9 sccm to about 16 sccm, a CO gas has a flow rate of about 50 sccm to about 250 sccm, an O
2
has has a flow rate of about 7 sccm to about 12 sccm, and an Ar gas has a flow rate of about 300 sccm to about 600 sccm.
In the present invention, the etching receipt has a high etching selectivity between the dielectric layer and the liner layer. When the dielectric layer is continuously etched to form deeper contact openings, the exposed liner layer can resist etching. Thus, no etched-through problem occurs. In this manner, the invention can performs a longer over-etching in order to prevent insufficient etching. In addition, the etching process is a one-step etching process. The etching is stop at the liner layer. Thereafter, the liner layer is removed. Thus, the fabrication of contact openings having different depths and different opening size is completed without changing the etching receipt in order to prevent the etched-though problem.
The present invention uses the C
5
F
8
/CO/O
2
/Ar etching gas to perform one-step etching process on the dielectric layer. Thus, contact openings having different depths and different opening sizes are formed. The etching uniformity is increased and the micro-loading effect is prevented.
Moreover, the present invention has a high etching selectivity between the photoresist layer and the silicon oxide layer. Thus, the thickness of the photoresist layer can be reduced. The exposure window is increased.
Furthermore, the present invention employs the one-step etching process using the C
5
F
8
/CO/O
2
/Ar etching gas. Thus, the present invention is not affected by the thickness of the dielectric layer. Therefore, with respect to the dielectric layer, the fabrication window of the present invention is increased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 6159839 (2000-12-01), Jeng et al.
patent: 6159862 (2000-12-01), Yamada et al.

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