Method of forming a line of high density floating gate transisto

Details Method of forming a line of high density floating gate transisto Method of forming a line of high density floating gate transisto

1996-07-09

1997-08-19

Niebling, John

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

257316, 438593, 438265, 438453, H01L 21265, H01L 218247

Patent

active

056588143

ABSTRACT:
A method of forming a line for floating gate transistors is described and which includes, providing a substrate having a plurality of discrete field oxide regions, and intervening active area regions therebetween; forming a first alternating series of floating gates over a first alternating series of active area regions; forming a second alternating series of floating gates over a second alternating series of active area regions, the second series of floating gates disposed in spaced, overlapping and partial covering relation relative to the first alternating series of floating gates; forming a layer of dielectric material over the first and second series of floating gates; and forming a control gate layer of electrically conductive material over the layer of dielectric material. The present invention further relates to a memory chip, and die having a line of floating gate transistors formed from the same method.

REFERENCES:
patent: 5306935 (1994-04-01), Esquivel et al.
patent: 5330924 (1994-07-01), Huang et al.
patent: 5378646 (1995-01-01), Huang et al.
patent: 5566106 (1996-10-01), Bergemont
patent: 5583360 (1996-12-01), Roth et al.
patent: 5604141 (1997-02-01), Bergemont

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