Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-07-17
2001-01-30
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S655000, C438S656000, C438S660000
Reexamination Certificate
active
06180519
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device which can prevent a dopant contained in a non-single-crystal silicon film for determining its conductivity type from diffusing into a metal silicide film, and therefore has improved device characteristics. The invention also relates to a method for manufacturing such a semiconductor device.
2. Description of the Related Art
FIG. 17
is a cross sectional view showing the construction of a first conventional semiconductor device, which is an NMOS transistor. In the drawing, reference numeral
1
denotes a semiconductor substrate;
2
, a device isolation oxide film formed on the semiconductor substrate
1
;
3
, source/drain regions formed in an active region surrounded by the device isolation oxide film
2
of the semiconductor substrate
1
;
4
, a gate oxide film formed on the semiconductor substrate
1
; and
5
, a gate electrode formed on the gate oxide film
4
. The gate electrode
5
is made up of a polycrystalline silicon film
6
doped with a dopant, e.g., phosphorous, for determining its conductivity type, a titanium silicide film
7
, and a tungsten silicide film which are stacked in the above order.
A method of manufacturing the NMOS transistor of the first prior art having the above-described construction will now be described in conjunction with
FIGS. 18A and 18B
. To begin with, the device isolation oxide film
2
is formed on the semiconductor substrate
1
by the LOCOS method. Next, the gate oxide film
4
having a thickness of 60 Å is formed by oxidizing the top surface of the semiconductor substrate
1
by, for example, thermal oxidation. Then, a polycrystalline silicon film
6
that is doped with phosphorous at a dose of 5×10
20
/cm
2
as a dopant for determining its conductivity type is formed at a thickness of, for example, 800 Å by CVD. A titanium silicide film
7
is then formed on the polycrystalline film
6
at a thickness of, for example, 150 Å by sputtering. This is followed by formation of a tungsten silicide film
8
at a thickness of, for example, 800 Å by sputtering (FIG.
18
A).
Thereafter, the gate electrode
5
is formed by etching a desired area of the tungsten silicide film
8
, the titanium silicide film
7
, and the polycrystalline silicon film
6
by use of a photolithography technique (FIG.
18
B). LDD layers are then formed by implanting, e.g., arsenic ions into the semiconductor substrate
1
being tilted at an angle of, e.g., about 40° under the conditions of, e.g., 30 keV and 40×10
13
/cm
2
. Side-wall oxide films
9
are formed by depositing a silicon oxide film at a thickness of 800 Å by, e.g., CVD, and etching back the thus-formed silicon oxide film. The source/drain regions
3
are formed by implanting, e.g., arsenic ions, into the semiconductor substrate
1
under the conditions of 50 kev and 40×10
15
/cm
2
. An NMOS transistor is completed by subjecting the substrate to a heat treatment of, e.g., 800° C. and 60 minutes (FIG.
17
).
FIG. 19
is a cross sectional view showing the construction of a second conventional semiconductor device, which is a DRAM cell. In the drawing, the same reference numerals are given to the corresponding elements of the first conventional semiconductor device, and the explanation thereof will be omitted here for brevity. Reference numeral
10
denotes diffusion layers formed in an active region surrounded by a device isolation oxide film
2
of a semiconductor substrate
1
;
11
, word lines formed on the semiconductor substrate
1
;
12
, a first interlayer insulation film so formed as to cover the word line
11
;
13
, a first contact hole formed through the first interlayer insulation film
12
to the top surface of the diffusion layer
10
; and
14
, a bit line so formed as to fill the first contact hole
13
. The bit line
14
is made up of a polycrystalline silicon film
15
doped with a dopant, e.g., phosphorous, for determining its conductivity type, a titanium silicide film
16
, and a tungsten silicide film
17
which are stacked in the above order.
Numeral
18
denotes a second interlayer insulation film so formed as to cover the bit line
14
;
19
, second contact holes formed through the first and second interlayer insulation films
12
and
18
to the top surface of the diffusion layer
10
; and
20
, capacitors so formed as to fill the respective second contact holes
19
. Each capacitor
20
is made up of a storage node
21
, a capacitor insulation film
22
, and a cell plate
23
which are stacked in this order.
A method of manufacturing the DRAM cell of the second prior art having the above-mentioned construction will now be described in conjunction with
FIGS. 20A-20C
. First, the device isolation oxide film
2
is formed on the semiconductor substrate
1
by the LOCOS method. Then, the word lines
11
is formed with, e.g., a polycrystalline silicon film. The diffusion layers
10
are then formed on the semiconductor substrate
1
by implanting, e.g., arsenic ions into the semiconductor substrate
1
. A first interlayer insulation film
12
is deposited at a thickness of 600 Å by, e.g., CVD. The first contact hole
13
is formed by etching a desired portion of the first interlayer insulation film
12
to the top surface of the diffusion layer
10
by photolithography (FIG.
20
A).
A polycrystalline silicon film
15
that is doped with a dopant, e.g., phosphorous, for determining its conductivity type at a dose of 5×10
20
/cm
2
is deposited at a thickness of 800 Å by CVD. A titanium silicide film
16
is deposited at a thickness of, e.g., 150 Å by sputtering, and a tungsten silicide film
17
is deposited at a thickness of, e.g., 800 Å by sputtering (FIG.
20
B). Subsequently, the bit line
14
is formed by etching prescribed portions of the polycrystalline silicon film
15
, the titanium silicide film
16
, and the tungsten silicide film
17
by photolithography (FIG.
20
C).
A second interlayer insulation film
18
is deposited at a thickness of 5,000 Å by, e.g., CVD, and the second contact hole
19
is formed by etching a desired portion of the first and second interlayer insulation films
12
and
18
to the top surface of the diffusion layer
10
by photolithography. The storage node
21
is then formed by depositing polycrystalline silicon that is doped with, e.g., phosphorous and has a thickness of 5,000 Å, and patterning the polycrystalline silicon film. The capacitor insulation film
22
is formed on the storage node
21
at a thickness of, e.g., 100 Å, and the cell plate
23
comprised of, e.g., a polycrystalline silicon film is formed at a thickness of 1,000 Å, thereby constituting the capacitor
20
. As a result, a DRAM cell is completed (FIG.
19
).
FIG. 21
is a cross sectional view showing the construction of a dual gate CMOS semiconductor of a third prior art. In this drawing, the same reference numerals are given to the corresponding elements of the conventional semiconductor devices set forth above, and the explanation thereof will be omitted here for brevity. Reference numeral
24
denotes a P well formed in an NMOS formation region I of a semiconductor substrate
1
;
25
, an N well formed in a PMOS formation region II of the semiconductor substrate
1
;
26
, N-type source/drain regions formed on the semiconductor substrate
1
in the NMOS formation region I; and
27
, P-type source/drain regions formed on the semiconductor substrate
1
in the PMOS formation region II.
Reference numeral
28
denotes an NMOS gate electrode formed in the NMOS formation region I. The NMOS gate electrode
28
comprises an N-type polycrystalline silicon film
29
doped with a dopant, e.g., phosphorous, for determining a first conductivity type, a titanium silicide film
7
, and a tungsten silicide film
8
which are stacked in the above order. Reference numeral
30
denotes a PMOS gate electrode formed in the PMOS formation region II. This PMOS gate electrode comprises a P-type po
Kuroi Takashi
Oda Hidekazu
Bowers Charles
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Pert Evan
LandOfFree
Method of forming a layered wiring structure including... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming a layered wiring structure including..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a layered wiring structure including... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2494997