Method of forming a landing pad on a semiconductor wafer

Details Method of forming a landing pad on a semiconductor wafer Method of forming a landing pad on a semiconductor wafer

1999-10-20

2001-08-21

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S253000, C438S396000, C438S596000, C438S612000, C438S631000, C438S639000, C438S647000

Reexamination Certificate

active

06277727

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor process, and more particularly, to a method of forming a landing pad on a semiconductor wafer.
2. Description of the Prior Art
The dynamic random access memory (DRAM) comprises a MOS transistor, a capacitor and a contact plug. The MOS transistor is used for transferring the electric charge, the capacitor is used for storing the charge to memorize information, and the contact plug is used as a node contact to electrically connect the MOS transistor and the capacitor. As devices of the semiconductor become smaller, the process for forming a contact hole to define the position of the contact plug becomes more difficult. Therefore, a landing pad is formed on the contact plug to ensure the connection between the contact plug and other devices.
Please refer to
FIG. 1
to FIG.
3
.
FIG. 1
to
FIG. 3
are the schematic diagrams of a prior art method of forming a landing pad
29
. The prior art method of forming the landing pad
29
is performed on a semiconductor wafer
10
. As shown in
FIG. 1
, the semiconductor wafer
10
comprises a silicon substrate
12
, a dielectric layer
20
made of silicon oxide positioned on the silicon substrate
12
, and a photo-resist layer
22
positioned on the dielectric layer
20
. The dielectric layer
20
comprises a first gate
14
and a second gate
16
within the dielectric layer
20
, and each of the gates
14
and
16
is surrounded by a spacer
18
made of silicon nitride. The photo-resist layer
22
comprises a hole
24
that penetrates to the surface of the dielectric layer
20
to define the position of the landing pad
29
.
In the formation of the landing pad
29
according to the prior art method, an anisotropic etching process is performed to vertically remove the dielectric layer
20
in the bottom of the hold
24
to form a contact hole
26
, as shown in FIG.
2
. Next, a photo-resist stripping process is performed to remove the photo-resist layer
22
on the semiconductor wafer
10
. Lastly, a conductive layer
28
is deposited in the contact hole
26
to completely fill the contact hole
26
, as shown in FIG.
3
. The bottom portion of the conductive layer
28
is used as a contact plug and the top portion of the conductive layer
28
is used as the landing pad
29
.
The dielectric layer
20
is made of silicon oxide, while the spacer
18
is made of silicon nitride. During the etching process, the etching selectivity ratio of silicon nitride to silicon oxide is very difficult to be adjusted to the optimal condition. So the surfaces of the first and second gates
14
,
16
and the spacers
18
will easily get damaged. Therefore the landing pad
29
will be formed at a position very close to the first and second gates
14
,
16
, which will cause an increase in the electrical coupling effect and affect the electrical performance of the semiconductor wafer
10
.
Please refer to
FIG. 4
to FIG.
8
.
FIG. 4
to
FIG. 8
are schematic diagrams of another prior method of forming a landing pad
29
. Another prior method of forming landing pad
29
is performed on a semiconductor wafer
10
using a first and a second photo-resist layers
22
,
27
to define the position of the landing pad
29
and the contact plug. As shown in
FIG. 4
, the semiconductor wafer
10
comprises a silicon substrate
12
, a dielectric layer
20
positioned on the silicon substrate
12
and a first photo-resist layer
22
positioned on the dielectric layer
20
. The dielectric layer
20
comprises a first gate
14
and a second gate
16
, and each of the first gate
14
and the second gate
16
is surrounded by a spacer
18
made of silicon nitride. The photo-resist layer
22
comprises a hole
24
that penetrates to the surface of the dielectric layer
20
to define the position of the landing pad
29
.
In the formation of the landing pad
29
in this method, an anisotropic etching process is performed to vertically remove the dielectric layer
20
in the bottom of the hold
24
to form a contact hole
26
, as shown in FIG.
5
. Next, a photo-resist stripping process is performed to remove the first photo-resist layer
22
from the semiconductor wafer
10
. Then, a conductive layer
28
is deposited in the contact hole
26
to completely fill the contact hole
26
, as shown in FIG.
6
. Afterward, a second photo-resist layer
27
is formed in a predetermined region on the semiconductor wafer
10
to define the position of the landing pad
29
, as shown in FIG.
7
. Lastly, the conductive layer
28
not covered by the second photo-resist layer
27
is removed to complete the formation of the landing pad
29
, as shown in FIG.
8
. The bottom portion of the conductive layer
28
is used as a contact plug and the top portion of the conductive layer
28
is used as the landing pad
29
.
By using the first photo-resist layer
22
to define the position of the contact hole
26
can prevent the surface of the first and second gate
14
,
16
and the spacer
18
from being damaged and prevent the increase in the electric coupling effect. However, the physical limitation will still increase the difficulty of the procedure. In order to define a smaller contact hole in aligning with the space between the two spacers
18
of the first gate and the second gate
16
,
14
, an advanced align machine is needed. But this will increase the process cost.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method of forming a landing pad on a semiconductor wafer to solve the above-mentioned problem.
In a preferred embodiment, the present invention relates to a method of forming a landing pad on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate, a dielectric layer on the silicon substrate, a passivation layer on the dielectric layer and a photo-resist layer on the passivation layer. The photo-resist layer comprises a hole penetrating to the surface of the passivation layer which defines the position of the landing pad. The method comprises:
performing a first anisotropic etching process through the hole to vertically remove the passivation layer and a predetermined thickness of the dielectric layer under the hole to form a recess;
performing a photo-resist stripping process to remove the photo-resist layer on the semiconductor wafer;
performing a deposition process to form a filling layer on the surface of the passivation layer and the recess;
performing an etch-back process to remove the filling layer on the bottom portion of the recess and partially remove the filling layer on the surrounding portion of the recess which forms a circular spacer on the surrounding portion of the recess;
performing a second anisotropic etching process to vertically remove the dielectric layer under the recess and down to the surface of the silicon substrate which forms a plug hole, over which the spacer surrounding the recess is used as a hard mask during the second anisotropic etching process; and
depositing a conductive layer in the recess and the plug hole to completely fill the recess and the plug hole which forms the landing pad.
It is an advantage of the present invention that only one photo-resist layer is needed to define the position of the landing pad and the increase in the electrical coupling effect caused by a small space between the landing pad and the gate can be avoided.
These and other objective of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.


REFERENCES:
patent: Re. 36398 (2000-10-01), Chan et al.
patent: 5622883 (1997-04-01), Kim
patent: 6080666 (2000-06-01), Lee et al.
patent: 6117757 (2000-09-01), Wang et al.
patent: 6121082 (2000-09-01), Linlin et al.
patent: 6150217 (2000-11-01), Chang et al.
patent: 6156608 (2000-12-01), Chen
patent: 6159843 (2000-12-01), Lin
NB9306413, IBM Technical Disclosure Bulletin, Jun. 1993, vol. 3

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