Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2000-10-12
2003-04-08
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S765000, C438S770000, C427S255600, C427S255190
Reexamination Certificate
active
06544907
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to integrated circuit fabrication and, more specifically, to a method of forming a gate oxide layer having a substantially uniform thickness.
BACKGROUND OF THE INVENTION
Over the last several decades, the electronics industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices. Moreover, a large variety of semiconductor devices having various applicability and numerous disciplines have been manufactured. One such silicon-based semiconductor device that has wide use is a metal-oxide-semiconductor (MOS) transistor.
An important step in the manufacturing of a MOS device is the formation of the gate oxide layer. The quality and uniformity of the gate oxide is critical to the proper operation of any MOS transistor. The gate oxide layer is typically grown in active regions of the device. In order to obtain reliable, high-quality gate oxides, the surface of the active area is often wet-etched to remove any residual oxide. The gate oxide is then grown slowly, typically through a wet oxidation in an oxygen, hydrogen and nitrogen ambient atmosphere or a dry oxidation in an oxygen and nitrogen ambient atmosphere. It is important to carefully control the growth of the gate oxide layer because the thickness and uniformity of the gate oxide layer can significantly impact the overall operation of the device being formed. For example, the drain current in a MOS transistor is inversely proportional to the gate oxide thickness at a given set of terminal voltages. In order to maintain proper transistor operation, which have shrunk well into the submicron range, the thickness of the gate oxide has shrunk in a corresponding fashion to maintain optimal and efficient operation of the transistors. Thus, it is highly desirable to make the gate oxide as thin as possible, taking into consideration the oxide breakdown and reliability considerations of the process and technology being used, while maintaining the robustness and electrical isolation integrity of the gate oxide.
As the overall thickness of the gate oxide layer continues to decrease (e.g., currently it is less than 1.7 nm), the thickness uniformity of the gate oxide layer (e.g., SiO
2
) becomes ever more critical and at the same time, more problematic. In the past when the gate oxide layer had a thickness of greater than about 10.0 nm, a 0.3 nm variation in gate oxide thickness over the surface of the gate oxide layer amounted to less than a 3 percent variation. However, as mentioned above, gate oxide thicknesses of less than about 1.7 nm are currently being manufactured, and this same 0.3 nm variation in thickness amounts to about a 17 percent variation. Such substantial variations in thickness over the surface of the gate oxide layer are highly undesirable and known to be quite problematic.
To overcome the above mentioned gate dielectric non-uniformity issues, the semiconductor manufacturing industry developed new gate oxide layer manufacturing techniques. Currently, the semiconductor manufacturing industry manufactures gate oxide layers at pressures ranging from about 10 Torr to about 15 Torr. However, forming gate oxides within these pressure ranges produce very non-uniform gate oxides. In previous thicker gate oxide designs this non-uniformity was acceptable as discussed above. But, with the ultra thin gate oxides required by today's semiconductor devices. This non-uniformity is unacceptable because it can decrease the device's overall quality and in some instances can even cause complete failure of the device.
Accordingly, what is needed in the art is a method of manufacturing a highly reliable, ultra thin and reliable oxide layer, that does not experience the problems associated with the prior art methods. The present invention addresses this need.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a method for manufacturing a high quality oxide layer having a uniform thickness. In one embodiment, the method includes providing a semiconductor substrate, and forming a gate oxide layer having a substantially uniform thickness on the semiconductor substrate and in a zone of pressure of less than about 4 Torr or greater than about 25 Torr.
It has been unexpectedly found that if the gate oxide layer is formed within these pressure ranges, a substantially uniform gate oxide layer can be formed. Thus, the uniformity problems associated with the prior art methods can be avoided. In fact, the flexibility in processing conditions, including the range of temperatures, range of fluid flows and type of fluid used, may be altered without substantially affecting the quality, thickness or uniformity of the oxide layer.
Another aspect of the invention provides a method of manufacturing an integrated circuit. The method of manufacturing the integrated circuit consists of (1) forming a transistor device over a substrate, including: forming a gate oxide layer having a substantially uniform thickness on the semiconductor substrate and in a zone of pressure of less than about 4 Torr or greater than about 25 Torr, and forming a transistor gate layer over the gate oxide layer, and (2) forming interconnect structures in dielectric layers located over the transistor device, the interconnect structures contacting the transistor device to form a completed integrated circuit.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
REFERENCES:
patent: 5940736 (1999-08-01), Brady et al.
patent: 6027984 (2000-02-01), Thakur et al.
patent: 6184110 (2001-02-01), Ono et al.
patent: 6248618 (2001-06-01), Quek et al.
patent: 6251800 (2001-06-01), Sun et al.
Ma Yi
Yang Edith
Agere Systems Inc.
Everhart Caridad
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