Method of forming a high aspect ratio shallow trench isolation

Details Method of forming a high aspect ratio shallow trench isolation Method of forming a high aspect ratio shallow trench isolation

2002-04-11

2004-12-07

Chen, Kin-Chan (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S723000, C438S756000

Reexamination Certificate

active

06828239

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to shallow trench isolation technology and, more particularly, to a method of forming a high aspect ratio shallow trench isolation.
2. Background
Escalating demands for high density and performance associated with ultra large scale integration require semiconductor devices with design features of 0.25 microns and under, e.g. 0.18 microns, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput. The reduction of design features to 0.25 microns and under challenges the limitations of conventional semiconductor technology for isolating active regions. One type of isolation is known as local oxidation of silicon (LOCOS) that disadvantageously results in bird's beak phenomenon. The other type of isolation is shallow trench isolation (STI) that provides a very good device-to-device isolation and reduces bird's beak phenomenon.
A STI process generally includes the following steps. First, using dry or wet etching with a mask, a trench is formed in a semiconductor substrate. Next, an insulating layer is deposited on the entire surface of the semiconductor substrate to fill the trench. The insulating layer is typically formed of silicon dioxide by chemical vapor deposition (CVD), such as atmospheric pressure chemical vapor deposition (APCVD), sub-atmospheric pressure chemical vapor deposition (SACVD) or high density plasma CVD (HDPCVD). Finally, CMP is used to planarize the insulating layer, thus the insulating layer remaining in the trench serves as a STI region.
Because of the increasing complexity of electronic devices, the dimensions of semiconductor devices are shrinking, while the width of STI regions is decreasing to 0.11 &mgr;m even less, and the aspect ratio of STI regions is increasing over 3. Even if a HDPCVD with good filling capability is employed, voids or seams still exist in the STI regions. Those defects cause short circuits between devices when conductive materials are deposited in subsequent processes, and thus reduce the lifetime of the device.
SUMMARY OF THE INVENTION
The object of the present invention is to solve the above-mentioned problems and to provide a method of forming a high aspect ratio shallow trench isolation.
The present invention discloses a method of forming a high aspect ratio shallow trench isolation in a semiconductor substrate, comprising the steps of forming a hard mask layer with a certain pattern on the semiconductor substrate, etching a portion of the semiconductor substrate not covered by the hard mask layer to form a high aspect ratio shallow trench in the semiconductor substrate; forming an oxide liner on the bottom and sidewall of the high aspect ratio shallow trench; performing a LPCVD to form a first oxide layer to fill the high aspect ratio shallow trench, a void being formed in the first oxide layer; etching a portion of the first oxide layer to a certain depth of the high aspect ratio shallow trench and to expose the void; and performing a HDPCVD to form a second oxide layer to fill the high aspect ratio shallow trench.
Furthermore, the invention proposes a method of forming a high aspect ratio shallow trench isolation in a semiconductor substrate, comprising the steps of forming a hard mask layer with a certain pattern on the semiconductor substrate, etching a portion of the semiconductor substrate not covered by the hard mask layer to form a high aspect ratio shallow trench in the semiconductor substrate; forming an oxide liner on the bottom and sidewall of the high aspect ratio shallow trench; performing a spin coating to form a glass layer to fill the high aspect ratio shallow trench; etching a portion of the glass layer to a certain depth of the high aspect ratio shallow trench; and performing a HDPCVD to form a oxide layer to fill the high aspect ratio shallow trench.


REFERENCES:
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patent: 6271147 (2001-08-01), Tseng
patent: 6337282 (2002-01-01), Kim et al.
patent: 6479405 (2002-11-01), Lee et al.
patent: 6501149 (2002-12-01), Hong
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S.Wolf, Silicon Processing for the VLSI Era , vol. 4, @2000 by Lattice Press, pp. 458, 459, 473.

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