Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Amorphous semiconductor
Reexamination Certificate
2005-03-08
2005-03-08
Blum, David S. (Department: 2813)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Amorphous semiconductor
C438S585000
Reexamination Certificate
active
06864161
ABSTRACT:
A process for forming a conductive gate structure for a sub-0.25 MOSFET technology, has been developed. The process features a conductive gate structure defined from a composite polysilicon or amorphous layer, which in turn is obtained via a dual deposition procedure. The first, or underlying silicon layer of the composite silicon layer, is deposited using a first silane flow rate which results in a silicon layer offering good performance characteristics but comprised with large silicon bumps. The second or overlying silicon layer of the composite silicon layer, is next deposited using a second silane flow rate, with the second silane flow greater than the silane flow used for the underlying silicon layer. The second silicon layer is formed with silicon bumps smaller in size than the silicon bumps of the first silicon layer. The narrow width, conductive gate structure, defined from the composite silicon layer via an anisotropic RIE procedure, provides performance characteristics greater than the performance characteristics of counterpart gate structures defined from silicon layers deposited using only the high, second silane flow rate. In addition the narrow width, conductive gate structure provides a reduced silicon bump size and thus improved yield, when compared to counterpart gate structures defined from silicon layers deposited using only the low, or first silane flow rate.
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Ackerman Stephen B.
Blum David S.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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