Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2002-06-26
2003-12-09
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S631000, C438S645000
Reexamination Certificate
active
06660573
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a semiconductor device comprising a gate electrode.
2. Description of the Related Art
There are two types of semiconductor memory devices. The first type is known as a RAM and the second type is known as a ROM. The RAM devices, such as a DRAM and an SRAM, are volatile (i.e., data is erased when power to the memory cell is turned off) and data is quickly inputted and outputted. The ROM is non-volatile and data is more slowly inputted and outputted. Among the ROM devices, demand is great for EEPROM (electrically erasable and programmable ROM) or a flash memory in which data is electrically inputted and outputted.
A fundamental structure in a semiconductor device is a transistor, which generally include a gate electrode. The gate electrode that is included in a respective cell of the semiconductor device is required to have a fine line width and a low resistance. Furthermore, the gate electrode needs to have a constant resistance value for all memory cell transistors across a wafer in order to improve reliability of inputting and outputting of data to and from the respective cell.
FIGS. 1A
to
1
E illustrate sectional views of stages in a conventional method of manufacturing a non-volatile memory device.
Referring to
FIG. 1A
, a gate oxide film (not shown) is formed on a semiconductor substrate
10
having a field area and an active area divided by a conventional isolation process. A conductive layer is formed on the gate oxide film in order to form a floating gate. After forming a dielectric film on the conductive layer, a polysilicon layer is formed on the dielectric film, which is used for a control gate. An insulating material, such as a nitride, is deposited to a thickness of 800-1500 Å on the polysilicon layer to form a hard mask layer.
The hard mask layer is patterned via a photolithography process to form a hard mask pattern
18
for patterning the gate electrode. The polysilicon layer, the dielectric film and the conductive layer are then continuously and anisotropically etched using the hard mask pattern
18
as an etching mask, thereby forming a gate structure
20
in which a gate oxide film pattern (not shown), the conductive pattern
12
, the dielectric pattern
14
and the polysilicon pattern
16
and the hard mask pattern
18
are stacked.
When the anisotropic etching is performed in order to form the gate structure
20
, the hard mask pattern
18
used as the etching mask also is partially etched due to the impact of an ion beam. However, the hard mask pattern
18
on the polysilicon layer pattern
16
is not etched to a uniform thickness throughout a whole pattern as a result of the etching. Accordingly, the hard mask pattern
18
has a non-uniform thickness within one gate structure
20
and also among various gate structures across a wafer.
Referring to
FIG. 1B
, an insulating material, such as an oxide, is deposited on the resultant structure shown in FIG.
1
A. Then, the insulating material is anisotropically etched to form a gate spacer
22
. A stopping layer
24
having a thickness of 500-800 Å is continuously formed on the gate spacer
22
, the semiconductor substrate
10
and the gate structure
20
. The stopping layer
24
includes an insulating material, such as a nitride. The stopping layer
24
indicates a stopping point when performing a subsequent polishing process for an insulating interlayer and is also used to self-align the contacts when forming contacts between the gate electrodes in a subsequent process.
Referring to
FIG. 1C
, as described above, a nitride film
26
, which includes the hard mask pattern
18
and the stopping layer
24
, is deposited on the respective polysilicon layer pattern
16
. Even though the stopping layer
24
is uniformly deposited, the nitride film
26
which includes the hard mask pattern and the stopping layer may not have a uniform thickness because of a non-uniform thickness of the hard mask pattern
18
remaining on the respective polysilicon layer pattern
16
.
As shown in
FIGS. 1C and 1D
, an insulating interlayer
28
is then formed to cover the resultant structure shown in
FIG. 1B
, which includes the stopping layer
24
. Then, a planarization process is performed to expose the polysilicon layer pattern
16
.
Referring firstly to
FIG. 1C
, the insulating interlayer
28
is formed in order to cover the resultant structure, including the stopping layer
24
. Then, the insulating interlayer
28
is chemically and mechanically polished to expose the stopping layer
24
, as shown in FIG.
1
C. In order to perform the polishing process for exposing the stopping layer
24
, a polishing rate of the nitride film should be slower than the polishing rate of the insulating interlayer oxide film
28
.
As described above, since the nitride film
26
, which is a top layer of the respective gate structure, has a non-uniform thickness, the nitride film
26
remaining on the polysilicon layer pattern
16
also has a non-uniform thickness after the chemical and mechanical polishing.
Referring now to
FIG. 1D
, the stopping layer
24
covering the hard mask pattern and the hard mask pattern
18
are removed to expose the polysilicon layer pattern
16
. That is, the nitride film
26
formed on the polysilicon layer pattern
16
is removed. The removal of the nitride film
26
is carried out via a dry etching or a wet etching process.
Since the nitride film
26
formed on the respective polysilicon layer pattern
16
has a non-uniform thickness, the polysilicon layer pattern
16
also has a non-uniform thickness. Similarly, an exposed portion of the polysilicon layer pattern
16
has a different area at different locations across the wafer
10
when the nitride film
26
is removed.
Particularly, when the dry etching is performed to remove the nitride film
26
, the polysilicon layer pattern
16
is continuously and gradually etched at a portion in which the nitride film
26
remaining on the polysilicon layer pattern
16
is thin so that the thickness of the polysilicon layer pattern
16
is reduced at that portion by the time the nitride film
26
is completely etched on the entire polysilicon layer pattern
16
. Furthermore, the gate spacer
22
is also etched thereby exposing a sidewall of the polysilicon layer pattern
16
. Therefore, after the nitride film
26
is completely etched, the thickness of the polysilicon layer pattern
16
is thinner at the portion where the thickness of the nitride film
26
on the polysilicon layer pattern
16
was thinner before the etching rather than at a portion where the thickness of the nitride film
26
was thicker before the etching.
If the nitride film
26
is removed by a wet etching, an etchant penetrates into the sidewall of the gate spacer
22
so that a portion of the stopping layer
24
formed on the sidewall of the gate spacer
22
is removed. At that time, the portion of the stopping layer
24
a
formed on the sidewall of the gate spacer
22
is removed non-uniformly due to the non-uniformity in the thickness of the nitride film
26
. Accordingly, the sidewall of the respective polysilicon layer pattern has a different exposed area.
Referring to
FIG. 1E
, a metal silicide layer
30
is selectively deposited on the exposed polysilicon layer pattern
16
to form a gate electrode. However, an area where the metal silicide layer
30
is formed is different at different locations because an area where the polysilicon layer pattern
16
is exposed is different at different locations on the wafer. Further, since the polysilicon layer pattern
16
has non-uniform thickness, the thickness of the gate electrode varies within one gate stack and also at different locations across the wafer.
As described above, in a conventional process of making a non-volatile memory device, since the polysilicon layer pattern for forming the gate electrode is formed non-unif
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