Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to nonconductive state
Reexamination Certificate
2005-03-08
2005-03-08
Deo, Duy-Vu N. (Department: 1765)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to nonconductive state
C438S601000, C257S529000
Reexamination Certificate
active
06864124
ABSTRACT:
A surface of a semiconductor substrate defined with at least one fuse area and at least one bonding pad area. A conductive layer with a thickness of 12 kÅ and a protective layer are sequentially formed on the surface of the semiconductor substrate. Then portions of the protective layer and portions of the conductive layer in the fuse area are etched to make the thickness for the remaining conductive layer in the fuse area be approximately 5 kÅ. Finally a dielectric layer is formed on the surface of the semiconductor substrate, and portions of the first dielectric layer and portions of the protective layer in the bonding pad area are etched until reaching the top surface of the conductive layer.
REFERENCES:
patent: 5844295 (1998-12-01), Tsukude et al.
patent: 6433438 (2002-08-01), Koubuchi et al.
patent: 6677226 (2004-01-01), Bowen et al.
patent: 6707129 (2004-03-01), Wang
Lee Chiu-Te
Wu Te-Yuan
Deo Duy-Vu N.
Hsu Winston
United Microelectronics Corp.
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