Method of forming a device isolation trench in an integrated...

Details Method of forming a device isolation trench in an integrated... Method of forming a device isolation trench in an integrated...

2002-02-22

2004-12-07

Deo, Duy-Vu (Department: 1765)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S425000, C438S435000, C438S436000, C438S691000, C438S692000

Reexamination Certificate

active

06828210

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 2001-09381, filed on Feb. 23, 2001, the contents of which are herein incorporated by reference in their entirety.
1. Field of the Invention
The present invention relates to a method of forming a semiconductor device and, more particularly, to a method of forming an isolation trench in an integrated circuit device.
2. Background of the Invention
Technology for forming device isolation trenches on a semiconductor substrate directly affects transistor characteristics and semiconductor device reliability. Poor device isolation causes leakage current, which wastes power supplied to semiconductor chips. Also, the possibility of undesirable device latch-up is heightened. Finally, poor device isolation causes problems of low noise margin, voltage shift, and crosstalk.
Local oxidation of silicon (LOCOS) has conventionally been used for device isolation. Patterned silicon nitride layer and pad oxide layer (for alleviating stress caused by the silicon nitride layer) are used to implant ions into an isolation region while masking an active region. Next, a thick field oxide layer is deposited to form a typical LOCOS structure. Unfortunately, LOCOS has several problems, e.g. bird's beak, which make it hard to fabricate a very large scale integrated circuit (VLSI). Threshold voltage increases and current driving capacity decreases.
In this regard, shallow trench isolation (STI) technique wherein a trench is formed by etching a semiconductor substrate and filling the trench with an insulating material to complete device isolation, has been used instead of LOCOS. Unfortunately, STI has some drawbacks as follows. The semiconductor substrate suffers from etching damage during etching the substrate to form the trench and oxidation of trench sidewall caused by subsequent oxidation processes, causing a physical and thermal stress. In this regard, recently, a thermal oxide layer is formed in the trench to cure etching damage and a nitride liner is formed on the thermal oxide layer as a buffer layer for stress.
The amount of wasted silicon is dependent upon the thickness of the thermal oxide layer. This produces a change in the trench upper edge profile that is capable of making the device malfunction. Thus the, defect rate is proportional to the thickness of the thermal oxide layer.
According to the foregoing conventional method, the trench is formed, and then a thick thermal oxide layer is formed to a thickness of, for example, 200 Å. Examination of the upper edge profile of a conventionally formed trench as shown in FIG.
8
. It may be seen that the profile of the trench's upper edge becomes sharp, and a gate oxide layer formed on the trench's upper edge is substantially thinner than in other areas. This makes it hard to form a gate oxide layer of constant thickness. As a result, reliability of the gate oxide layer cannot be ensured. Further, if a strong electric field is applied, the thin gate oxide layer can break down.
On the other hand, if a thin thermal oxide layer, for example, 100 Å, is formed in the trench, the semiconductor substrate profile of the trench's upper edge is rounded and thus improved. Also, it is possible to prevent formation of a thin gate oxide layer at the trench's upper edge. However, charged particles, i.e., negative or positive particles (impurity materials) which are caused by defects at the interface between the nitride liner and the thermal oxide layer or defects of the layers during transistor operation by applying electric field, are not discharged to outside due to the nitride liner, but are diffused instead into the semiconductor substrate (active the region) through the thin thermal oxide layer. This is because the thermal oxide layer is too thin to trap the impurity materials sufficiently. When the positive ions reach the substrate at the trench sidewall, a transistor's electrical characteristics deteriorate. Thus, stand-by current becomes defective because the positive ions penetrate the substrate at the trench sidewall through the thin thermal oxide layer due to a tunneling phenomenon.
In a trench structure employing a conventional thermal oxide layer and nitride liner, device operation characteristics are largely dependent upon the thickness of the thermal oxide layer. Thus, it is very hard to achieve both good stress characteristic and good trench profile.
Therefore, an object of the present invention is to provide a method of forming an isolation trench, in which device characteristics are scarcely dependent upon the thickness of the thermal oxide layer. In other words, the object is to provide a method of forming a trench which can prevent deterioration of transistor characteristics.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, there is provided a method of forming a trench isolation including a nitride liner in a semiconductor substrate. The substrate is etched to a predetermined depth to form a trench. A conformal material layer is formed on both the sidewall and the bottom of the trench. A thin thermal oxide layer is grown between the conformal material layer and the substrate through a thermal oxide process for preventing etch damage during etching. The nitride liner is formed on the material layer. Trench isolation material is used to fill the trench.
Overall thickness of the conformal material layer and the thermal oxide layer is enough to prevent penetration of impurity material. The conformal material layer is formed to a thickness of 50Å-400 Å, and the thermal oxide layer is formed to a thickness of 20Å-150 Å. The conformal material is selected from a group consisting of high temperature oxide (HTO), middle temperature oxide (MTO), aluminum trioxide (Al
2
O
3
), and tantalum pentaoxide (Ta
2
O
5
).
More specifically, the HTO layer is formed at a temperature of 800° C. using SiH
4
, O
2
, and N
2
as a source gas via a chemical vapor deposition (CVD) technique. The MTO layer is formed at a temperature of 730° C. using SiH
4
, O
2
, and N
2
as a source gas via the CVD technique. The aluminum trioxide layer is formed at a temperature of 350° C. under a pressure of 0.5 Torr using Al (CH
3
)
3
of 150 sccm as a source gas and H
2
O of 150 sccm through the CVD technique. The tantalum pentaoxide layer is formed using Ta(OC
2
H
5
)
5
as a source gas and O
2
through the CVD technique.
An insulation layer for filling the trench is made of high-density plasma (HDP) oxide or borophosphosilicate glass (BPSG). If the trench is filled with HDP oxide, a middle temperature oxide (MTO) layer is preferably further formed so as to protect the nitride liner.
Preferably, the trench is formed by the steps of forming a pad oxide layer and a mask nitride layer on the substrate, patterning the mask nitride layer and pad oxide layer using a predetermined photoresist pattern in which a device isolation area is defined, and etching the substrate to a predetermined depth using the patterned mask nitride and pad oxide layers.


REFERENCES:
patent: 5190889 (1993-03-01), Poon et al.
patent: 6037018 (2000-03-01), Jang et al.
patent: 6046487 (2000-04-01), Benedict et al.
patent: 6140208 (2000-10-01), Agahi et al.
patent: 6180493 (2001-01-01), Chu
patent: 6251735 (2001-06-01), Lou
patent: 6461937 (2002-10-01), Kim et al.
patent: 2002/0117731 (2002-08-01), Kim et al.

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