Method of forming a damascene structure with integrated...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S678000, C257SE21575

Reexamination Certificate

active

10942302

ABSTRACT:
Methods are provided for forming a circuit component on a workpiece substrate. The methods comprise the steps of depositing a dielectric material over the substrate; etching a pattern through the dielectric material to expose a portion of the substrate; depositing a barrier metal over the dielectric material and the exposed portion of the substrate; depositing a conductive metal over the barrier metal, the deposited conductive metal having a thickness sufficient to fill the etched pattern; planarizing the conductive metal to form a planar metal layer; and polishing the metal layer and the barrier metal in a single polishing step using an abrasive-free polish until the dielectric material surrounding the pattern is exposed.

REFERENCES:
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patent: 2003/0132120 (2003-07-01), Emesh et al.
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Kondo et al Complete Abrasive Free process for Copper Damascene Interconnetion, pp. 253-255, IEEE 2000.
Kondo, et al.; “Complete-Abrasive-Free Process for Copper Damascene Interconnection”; IEEE 2000; pp. 253-255;Central Research Laboratory, Hitachi, Ltd.,; Tokyo, Japan.
Yamaguchi et al.; “A 7 level Metallization with Cu Damascene Process using Newly Developed Abrasive Free Polishing”;IEEE 2000; pp. 264-266;Device Development Center, Hitachi, Ltd.; Tokyo, Japan.
Li et al.; “A Low Cost and Residue-Free Abrasive-Free Copper CMP Process With Low Dishing, Erosion and Oxide Loss”;IEEE 2001; pp. 137-139;CMP Business Group, Applied Materials; Santa Clara, California, USA.

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