Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-08-19
2002-09-24
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S299000, C438S630000, C438S632000, C438S642000, C438S664000, C438S682000
Reexamination Certificate
active
06455420
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method of forming a compound film of a semiconductor and a metal on a surface of a semiconductor region by self alignment.
2. Description of the Related Art
To micropattern a semiconductor device, e.g., a MOS transistor, and to increase its operation speed, the resistance of an impurity region formed in a semiconductor substrate and of an interconnection made of a semiconductor must be decreased. For this purpose, a structure in which a compound film of a semiconductor and a metal is formed on a surface of a semiconductor region by self alignment has been studied.
FIG. 1
shows the first related art of a method of manufacturing a MOS transistor having such a compound film. According to the first related art, an SiO
2
film
12
is selectively formed on a surface of an Si substrate
11
to determine an isolation region. A well
13
is formed in the Si substrate
11
, and an SiO
2
film
14
serving as a gate oxide film is formed on the surface of an active region surrounded by the SiO
2
film
12
.
Thereafter, a gate electrode is formed by a poly-Si film
15
or the like. A lightly doped impurity region
16
constituting a source-drain region having an LDD structure is formed. A side wall spacer constituted by an SiN film
17
is formed on a side face of the poly-Si film
15
. A heavily doped impurity region
18
constituting a source-drain region having the LDD structure is formed, and a Ti film (not shown) is deposited on the entire surface of the Si substrate
11
.
Thereafter, silicidation is caused at the interface between the Si substrate
11
or the poly-Si film
15
and the Ti film by a comparatively low-temperature first-step annealing, to form a comparatively high-resistance C49-phase TiSi
2
film (not shown). The unreacted Ti film and the like remaining on the SiO
2
film
12
and the SiN film
17
are removed. Phase transition of the C49-phase TiSi
2
film to a comparatively low-resistance C54-phase TiSi
2
film
21
is performed by a comparatively high-temperature second-step annealing.
The two-steps annealing is performed in this manner due to the following reason. If a high-temperature annealing that can immediately form the low-resistance C54-phase TiSi
2
film
21
is performed from the beginning, an Si is supplied from the impurity region
18
also to the Ti film on the SiO
2
film
12
and the SiN film
17
, to form TiSi
2
films
21
on the SiO
2
film
12
and the SiN film
17
as well. Then, for instance, the TiSi
2
film
21
on the poly-Si film
15
and the TiSi
2
film
21
on the impurity region
18
may be short-circuited through the TiSi
2
film
21
on the SiN film
17
.
After the C54-phase TiSi
2
film
21
is formed, an SiO
2
film
22
, an SiO
2
-based film
23
, and an SiO2 film
24
serving as an interlayer insulating film are sequentially deposited, and contact holes
25
are formed to extend through the SiO
2
film
24
, the SiO
2
-based film
23
, and the SiO
2
film
22
. The contact holes
25
are filled with W films
26
or the like, and upper layer interconnections (not shown) and the like are formed, thus completing this MOS transistor.
FIG. 2
shows the second related art of the MOS transistor manufacturing method. In the second related art, after contact holes
25
are formed, an impurity is ion-implanted through the contact holes
25
to form an impurity region
27
, having the same conductivity type as that of impurity regions
16
and
18
, in the Si substrate
11
. The impurity is activated by an annealing, and the contact holes
25
are filled with W films
26
. Except for that, steps substantially identical to those of the first related art shown in
FIG. 1
are performed.
In the first related art described above, as shown in
FIG. 1
, when the positions of the contact holes
25
are displaced due to an alignment error or the like of a mask in a photolithography for forming the contact holes
25
, and the contact holes
25
are located on the end portions of the SiO
2
film
12
, the SiO
2
film
12
is also etched together with the SiO
2
film
24
, the SiO
2
-based film
23
, and the SiO
2
film
22
.
As a result, a contact portion
28
is formed where the W films
26
that fill the contact holes
25
, and the well
13
come into contact with each other directly and not through the impurity region
18
. Even if the contact holes
25
are located on the SiN film
17
, since the etching selectivity of the SiO
2
film
22
, the SiO
2
-based film
23
, and the SiO
2
film
24
with respect to the SiN film
17
can be increased, the SiN film
17
will not be etched together with the SiO
2
film
22
, the SiO
2
-based film
23
, and the SiO
2
film
24
.
When the contact portion
28
is formed, even if the impurity region
18
and the well
13
are reverse-biased, a leakage current flows between the W films
26
and the well
13
through the contact portion
28
. In order to prevent the contact holes
25
from locating on the end portions of the SiO
2
film
12
even if a mask alignment error or the like occurs during the photolithography, the area of the impurity region
18
cannot but be increased. This makes it impossible to manufacture a micropatterned MOS transistor.
In contrast to this, in the second related art described above, since the impurity region
27
is formed as shown in
FIG. 2
, a leakage current between the W films
26
and the well
13
is prevented, and the alignment error of the contact holes
25
is compensated. In the second related art, however, after the low-resistance C54-phase TiSi
2
film
21
is formed, an annealing for activating the impurity in the impurity region
27
is performed. This annealing agglomerates the TiSi
2
film
21
to increase its resistance.
An increase in resistance of the TiSi
2
film
21
caused by the annealing occurs conspicuously particularly on the poly-Si film
15
having a small line width. On the poly-Si film
15
having a line width of 0.15 &mgr;m, the sheet resistance which has been equal to or lower than 10 &OHgr;/ increases to about 50 &OHgr;/ upon the annealing at 850° C. for 30 seconds. Accordingly, in the second related art, a thinning effect occurs in the TiSi
2
film
21
due to the annealing that aims at activating the impurity for forming the impurity region
27
.
In the first related art described above, the area of the impurity region
18
and the like cannot be decreased, and a micropatterned semiconductor device cannot accordingly be manufactured. In the second related art described above, a low-resistance TiSi
2
film
21
cannot be formed, and a high-speed semiconductor device cannot accordingly be manufactured. In fine, a micropatterned and high-speed semiconductor device cannot be manufactured with either the first or second related art described above.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method capable of manufacturing a micropatterned and high-speed semiconductor device at a low cost.
In a semiconductor device manufacturing method according to the present invention, a relatively high-resistance low-resistance second compound film by a relatively high-temperature second annealing which is done after an insulating film is formed. Hence, the annealing aiming at decreasing a resistance of the compound film can also serve as another annealing as well, and the number of times of annealing applied to the compound film the resistance of which has been decreased is small. As a result, a thinning effect of the compound film caused by an agglomeration can be suppressed, and a sheet resistance of the semiconductor region and the compound film can be decreased, while the number of manufacturing steps is small. A micropatterned and high-speed semiconductor device can accordingly be manufactured at a low cost.
In a preferred semiconductor device manufacturing method according to the present invention, the annealing aiming at decreasing the resistance of the compound film also serves as an ann
Nguyen Tuan H.
Pham Thanhha
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