Method of forming a CMOS device with stressor source/drain...

Details Method of forming a CMOS device with stressor source/drain... Method of forming a CMOS device with stressor source/drain...

2006-02-08

2008-11-04

Smith, Zandra V. (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S199000, C438S275000, C257SE21198

Reexamination Certificate

active

07446026

ABSTRACT:
A method for forming a semiconductor device includes providing a semiconductor substrate having a first doped region and a second doped region, providing a dielectric over the first doped region and the second doped region, and forming a first gate stack over the dielectric over at least a portion of the first doped region. The first gate stack includes a metal portion over the dielectric, a first in situ doped semiconductor portion over the metal portion, and a first blocking cap over the in situ doped semiconductor portion. The method further includes performing implantations to form source/drain regions adjacent the first and second gate stack, where the first blocking cap has a thickness sufficient to substantially block implant dopants from entering the first in situ doped semiconductor portion. Source/drain embedded stressors are also formed.

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PCT/US07/60145 International Search Report and Written Opinion mailed Aug. 26, 2008.

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