Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2005-03-01
2005-03-01
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S656000, C438S680000, C438S683000, C438S685000
Reexamination Certificate
active
06861356
ABSTRACT:
There is provided a method of forming a barrier metal which is designed to be interposed between a metal layer and an insulating layer, both constituting a multi-layered structure of semiconductor device, the method comprising the steps of positioning a substrate having the insulating layer formed thereon at a predetermined position inside a processing vessel forming a processing space, and alternately introducing a gas containing a refractory metallic atom, a gas containing Si atom and a gas containing N atom into the processing vessel under a predetermined processing pressure, thereby allowing a refractory metal nitride or a refractory metal silicon nitride to be deposited on the insulating layer by way of atomic layer deposition.
REFERENCES:
patent: 4389973 (1983-06-01), Suntola et al.
patent: 5010032 (1991-04-01), Tang et al.
patent: 5066615 (1991-11-01), Brady et al.
patent: 5106786 (1992-04-01), Brady et al.
patent: 5134451 (1992-07-01), Katoh
patent: 5796166 (1998-08-01), Agnello et al.
patent: 5817572 (1998-10-01), Chiang et al.
patent: 5888588 (1999-03-01), Nagabushnam et al.
patent: 5916634 (1999-06-01), Fleming et al.
patent: 5962904 (1999-10-01), Hu
patent: 6015590 (2000-01-01), Suntola et al.
patent: 6051492 (2000-04-01), Park et al.
patent: 6060361 (2000-05-01), Lee
patent: 6084279 (2000-07-01), Nguyen et al.
patent: 6096630 (2000-08-01), Byun et al.
patent: 6103607 (2000-08-01), Kizilayalli et al.
patent: 6200893 (2001-03-01), Sneh
patent: 6482733 (2002-11-01), Raaijmakers et al.
patent: 6573184 (2003-06-01), Park
patent: 6602784 (2003-08-01), Sneh
patent: 6656835 (2003-12-01), Marsh et al.
patent: 20010034123 (2001-10-01), Jeon et al.
patent: 20030013320 (2003-01-01), Kim et al.
patent: 20030064153 (2003-04-01), Solanki et al.
patent: 64-5015 (1964-01-01), None
patent: 62-188268 (1987-08-01), None
patent: 5-129231 (1993-05-01), None
patent: 8-293604 (1996-11-01), None
patent: 9-186102 (1997-07-01), None
patent: 9-199445 (1997-07-01), None
patent: 9-260306 (1997-10-01), None
patent: 10-209073 (1998-08-01), None
patent: 10-294314 (1998-11-01), None
patent: 11-26394 (1999-01-01), None
patent: 11-26757 (1999-01-01), None
patent: WO9617104 (1996-06-01), None
Kasai et al., “WNx/Poly-Si Gate Technology for Future High Speed Deep Submicron CMOS LSIs”,IEEE IEDM Tech. Digest, 1994, pp. 497-500.
Wolf, S., “Silicon Processing for the VLSI Era”, vol. 2, Lattice Press, 1990, pp. 192-193, 587-591.
Matsuse Kimihiro
Otsuki Hayashi
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Quach T. N.
Tokyo Electron Limited
LandOfFree
Method of forming a barrier film and method of forming... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming a barrier film and method of forming..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a barrier film and method of forming... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3426270