Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1997-01-22
1998-05-26
Quach, T. N.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438655, 438657, 438664, H01L 21283, H01L 21324
Patent
active
057563926
ABSTRACT:
An method for the formation of polycide used for the gate electrode or interconnection metallization in semiconductor integrated circuit devices has been developed. The polycide is formed from doped amorphous silicon deposited from SiH.sub.4 and PH.sub.3 and tungsten silicide deposited from dichlorosilane (SiH.sub.2 Cl.sub.2 and WF.sub.6, followed by conventional RIE patterning. The key feature, annealing of the polycide structure by a combination of RTA (Rapid Thermal Anneal) in a nitrogen ambient, and then a furnace anneal in an oxygen ambient prevents deleterious sidewall growth on the polycide structure and results in a highly manufacturable process having high yield.
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Chen Bu-Fang
Chen Chih-Ming
Liaw Jhon-Jhy
Lu Hsiang-Fan
Ackerman Stephen B.
Quach T. N.
Saile George O.
Taiwan Semiconductor Manuacturing Company, Ltd.
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