Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2003-05-21
2004-08-31
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C260S66500B, C260S66500B, C260S66500B, C260S66500B, C260S998200, C260S66500B, C260S66500B
Reexamination Certificate
active
06784103
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductors, and more specifically, to the formation nanocrystal structures for semiconductor optical and memory devices.
BACKGROUND OF THE INVENTION
Memory circuits are frequently implemented with cells having a floating gate transistor wherein the floating gate is formed from a uniform layer of material such as polysilicon. In such structures, a thin tunnel dielectric layer beneath the floating gate presents the problem of charge leakage from the floating gate to the underlying channel through defects in the thin tunnel dielectric layer. Such charge leakage can lead to degradation of the memory state stored within the device and is therefore undesirable. In order to avoid such charge leakage, the thickness of tunnel dielectric is often increased. However, charge transfer across thicker tunnel dielectric requires higher (programming and erasing) voltages for storing and removing charge from the floating gate. In many cases, higher programming voltages require the implementation of charge pumps on integrated circuits in order to increase the supply voltage to meet programming voltage requirements. Such charge pumps consume a significant amount of die area for the integrated circuit and therefore reduce the memory array area efficiency and increase overall costs.
In order to reduce the required thickness of the tunnel dielectric and improve the area efficiency of the memory structures by reducing the need for charge pumps, the uniform layer of material used for the floating gate may be replaced with a plurality of silicon nanocrystals, which operate as isolated charge storage elements. In combination, the plurality of nanocrystals provide adequate charge storage capacity while remaining physically isolated from each other such that any leakage occurring with respect to a single nanocrystal via a local underlying defect does not cause charge to be drained from other nanocrystals (by controlling average spacing between nanocrystals, it can be ensured that there is no lateral charge flow between nanocrystals in the floating gate). As such, thinner tunnel dielectrics can be used in these device structures. The effects of leakage occurring in such thin tunnel dielectric devices does not cause the loss of state information that occurs in devices that include a uniform-layer floating gate.
A limiting factor in fabrication of devices that include floating gates made up of a plurality of nanocrystals relates to controlling of the number density, size, area coverage and uniformity of the nanocrystals within the floating gate structure. The number density of the nanocrystals is important in the determination of the change in the threshold voltage for the device between the states where the floating gate is charged or discharged. Higher densities are desirable as they lead to an increased change in threshold voltage when the number of charges per storage element is fixed. Typically a nanocrystal density of 10
12
cm
−2
and a mean size of about 5 nm (area fraction of about twenty percent) is desired for optimal device operation. With a limited density of isolated storage elements, the charge density per nanocrystal, or number of carriers that each nanocrystal must retain, is forced to an elevated level. The higher storage density per nanocrystal typically leads to charge loss from individual nanocrystals, thus degrading the overall charge retention characteristics of the floating gate. In addition to this limitation, lower nanocrystal densities require longer programming times as a longer time period is required for forcing subsequent charge carriers into each nanocrystal after an initial carrier has been stored and because lower densities imply smaller charge capture probability for carriers injected from the substrate. Furthermore, the time required for adding subsequent carriers continues to increase as the charge density per nanocrystal is elevated.
In one prior art technique for forming nanocrystals, ion implantation is used to implant silicon atoms into a dielectric material. Following implantation, an annealing step causes these implanted silicon atoms to group together through phase separation to form the nanocrystals. Problems arise using such a technique due to the difficulty in controlling the depth at which the silicon nanocrystals are formed due to the phase segregation in the dielectric material. Because the depth at which the isolation storage elements are formed dramatically affects the electrical characteristics of the resulting device, ion implantation does not provide the level of control desired in a manufacturing situation.
In another prior technique for forming the nanocrystals, a thin layer of amorphous silicon is deposited on the tunnel dielectric material. A subsequent annealing step is used to recrystalize the amorphous silicon into the nanocrystals. In order to produce nanocrystals of a desired density and size, the layer of amorphous silicon should be deposited such that it is on the order of 7-10 angstroms in thickness. Deposition of such thin layers of amorphous silicon is hard to control and therefore impractical in a manufacturing process. In addition to such control issues, additional problems may arise due to preexisting crystalline zones within the amorphous silicon layer. Such preexisting crystallites serve as nucleation sites for crystal growth, which deleteriously interferes with the spontaneous crystal growth desired for formation of the nanocrystals.
In other prior techniques for forming nanocrystals, chemical vapor deposition (CVD) techniques such as low pressure chemical vapor deposition (LPCVD) are used to nucleate and grow the nanocrystals directly on the tunnel oxide using silane and nanocrystal densities of the order of 10
12
cm
−2
have been reported. In this approach substantial surface modification has to be performed to facilitate nucleation and the nanocrystal density is very sensitive to the deliberately introduced surface bonding modification. This is particularly so in a manufacturing environment where there is often a delay period between the surface modification and the processing of nanocrystals during which time the surface condition can change to an unknown extent. Thus, this approach makes the nanocrystal characteristics very sensitive to the surface bonding structure while a manufacturable solution should be tolerable to a wide range of surface conditions.
Cold wall Ultra High Vacuum Chemical Vapor Deposition (UHVCVD) using a disilane precursor has also been shown to yield nanocrystal densities of the order of 10
12
cm
−2
. Problems with this approach include prohibitively long deposition times with most of the expensive precursor gas wasted as an exhaust material byproduct. This is because the sticking coefficient of disilane is extremely small on oxide surfaces implying a long time to nucleate nanocrystals and is also small on silicon nanocrystals that leads to slow growth.
REFERENCES:
patent: 5234862 (1993-08-01), Aketagawa et al.
patent: 5830538 (1998-11-01), Gates et al.
patent: 5850064 (1998-12-01), Goldstein
patent: 6001175 (1999-12-01), Maruyama et al.
patent: 6060743 (2000-05-01), Sugiyama et al.
patent: 6090666 (2000-07-01), Ueda et al.
patent: 6268041 (2001-07-01), Goldstein
patent: 6297095 (2001-10-01), Muralidhar et al.
patent: 6344403 (2002-02-01), Madhukar et al.
patent: 6455372 (2002-09-01), Weimer
patent: 2003/0183901 (2003-10-01), Kanda et al.
patent: 2004/0086640 (2004-05-01), Luo et al.
F. Mazen et al., Control of Silicon Quantum Dots nucleation and growth by CVD, Materials Research Society Symposium Proceedings, 2003, pp. F1.9.1-F1.9.6, vol. 737, Material Research Society.
Masato Oishi et al., Fabrication of Silicon Nano-Crystal Dots on SiO2by Ultrahigh-Vacuum Chemical Vapor Disposition, Materials Research SOciety Symposium Proceedings, 2001, vol. 638, Materials Research Society.
Madhukar, Sucharita et al.; “CVD Growth of Si Nanocrystals on Dielectric Surfaces for Nanocrystal Floating Gate Memory Application”; Materials Resea
Merchant Tushar P.
Muralidhar Ramachandran
Rao Rajesh A.
Anya Igwe U.
Balconi-Lamica Michael
Freescale Semiconductor Inc.
King Robert I.
Smith Matthew
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