Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1999-10-22
2001-03-20
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S269000, C438S404000, C438S405000, C438S413000
Reexamination Certificate
active
06204098
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the manufacturing of semiconductive chips including at least one area corresponding to power components and at least one area corresponding to logic components.
2. Discussion of the Related Art
For a long time, designers and manufacturers of semiconductor components have attempted to integrate, on the same chip logic circuits and at least one vertical power component having a first electrode located on the upper surface and a second electrode located on the lower surface of the chip. The problem of the isolation of the logic circuits powered by low voltages and conducting small currents, which are likely to be disturbed by the high voltages and currents in the power components, then arises. Conventional solutions, which consist of using junction isolations, are never totally efficient. It has thus been devised to form the logic circuits in a portion dielectrically insulated from the substrate in which the power components are made. An example of such a solution has been described in 1985 by Joseph Borel in European patent 0220974. However, although they are theoretically attractive, the various suggested structures have had difficulties to be implemented, whereby, in practice, no power components associated with logic circuits with a complete or partial dielectric insulation from the power portion are presently available for sale.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a solution to this problem which in particular fulfils the following criteria:
there is no disturbed interface in the vertical area corresponding to the power components; and
the apparent surface of the portion of the chip intended for making the logic circuits is at the same level as the upper surface of the chip intended for making a power component.
This second criterion has a great practical importance. Indeed, performing photolithography operations on surfaces located in distinct planes complicates manufacturing processes.
To achieve this and other objects, the present invention provides a method of forming an insulated well in an upper portion of a silicon substrate, including the steps of providing a structure of silicon-on-insulator type including a silicon substrate, an insulating layer, and a thin single-crystal silicon layer; removing the insulating layer and the thin silicon layer outside locations where the insulated well is desired to be formed; growing an epitaxial layer; performing a planarization; and making a vertical insulating wall above the periphery of the maintained portion of the thin insulating layer.
According to an embodiment of the present invention, the epitaxial layer has a thickness greater than 10 &mgr;m.
According to an embodiment of the present invention, the thickness of the epitaxial layer is on the order of 40 to 60 &mgr;m.
According to an embodiment of the present invention, the step of etching the thin single-crystal silicon layer and the insulating layer includes the steps of forming a layer of a first material selectively etchable with respect to silicon; depositing and delimiting a resist mask; etching the layer of the first material and the thin silicon layer; depositing a new resist layer extending beyond the layers already etched; etching the insulating layer under the new resist layer; removing the resist and the remaining upper portion of the layer of the first material.
According to an embodiment of the present invention, the insulating layer and the layer of the first material are silicon oxide layers.
According to an embodiment of the present invention, the forming of the vertical insulating wall includes the steps of forming a layer of a second material of a first thickness; forming in the layer of the second material a first opening at the location of the wall which is desired to be formed; forming a layer of a third material of a second thickness; etching the layer of the second material substantially in the middle of the first opening; opening the underlying silicon down to the bottom oxide insulting layer; forming an insulation on the opening walls; filling with polysilicon.
According to an embodiment of the present invention, the second and third materials are silicon oxide and the second thickness is smaller than the first thickness.
According to an embodiment of the present invention, the thin single-crystal silicon layer is heavily doped of a selected conductivity type, the epitaxial layer being of the same conductivity type, with a low doping level.
REFERENCES:
patent: 4507158 (1985-03-01), Kamins et al.
patent: 4908328 (1990-03-01), Hu et al.
patent: 4963505 (1990-10-01), Fujii et al.
patent: 5049521 (1991-09-01), Belanger et al.
patent: 5164218 (1992-11-01), Tsuruta et al.
patent: 5433168 (1995-07-01), Yonehara
patent: 5700712 (1997-12-01), Schwalke
patent: 5767562 (1998-06-01), Yamashita
patent: 5811315 (1998-09-01), Yindepool et al.
patent: 5825067 (1998-10-01), Takeuchi et al.
patent: 6008687 (1999-12-01), Orita et al.
Patent Abstracts of Japan, vol. 097, No. 012, Dec. 25, 1997 & JP-A-09 223730 (Denso Corp.).
Patent Abstracts of Japan, vol. 097, No. 004, Apr. 30, 1997 & JP-A-08 330581 (Nippondenso Co., Ltd.).
Galanthay Theodore E.
Morris James H.
Niebling John F.
Simkovic Viktor
STMicroelectronics S.A.
LandOfFree
Method of formation in a silicon wafer of an insulated well does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of formation in a silicon wafer of an insulated well, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of formation in a silicon wafer of an insulated well will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2492678