Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
2007-08-22
2010-10-26
Lane, Jack A (Department: 2185)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C711S103000, C711S202000, C365S051000, C365S063000, C365S230030, C365S230060
Reexamination Certificate
active
07822910
ABSTRACT:
Embodiments of the invention may generally provide techniques that allow mapping of memory devices in a multi-chip package (MCP) to memory segments of an address space. For some embodiments, a multi-bit device ID, which corresponds to a memory segment to which that device is mapped, is loaded for each memory device. Higher order address bits are then compared to the device IDs assigned to each device. An internally generated chip select line is asserted for a device having a match between the address bits and its device ID.
REFERENCES:
patent: 4392212 (1983-07-01), Miyasaka et al.
patent: 4982265 (1991-01-01), Watanabe et al.
patent: 5345412 (1994-09-01), Shiratsuchi
patent: 5430859 (1995-07-01), Norman et al.
patent: 5587341 (1996-12-01), Masayuki et al.
patent: 7236423 (2007-06-01), Sohn et al.
patent: 2007/0126105 (2007-06-01), Yamada et al.
patent: 2007/0223290 (2007-09-01), Sohn et al.
patent: 2009/0052270 (2009-02-01), Kao
Lane Jack A
Patterson & Sheridan LLP
Qimonda North America Corp.
LandOfFree
Method of flexible memory segment assignment using a single... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of flexible memory segment assignment using a single..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of flexible memory segment assignment using a single... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4213689