Method of flexible clock placement for integrated circuit...

Details Method of flexible clock placement for integrated circuit... Method of flexible clock placement for integrated circuit...

2008-04-01

2008-04-01

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

07353485

ABSTRACT:
A method of global clock placement for a circuit design to be implemented on a programmable logic device (PLD) can include identifying clock properties for the circuit design and identifying physical clock region attributes for the PLD. The method further can include specifying an Integer Linear Programming formulation (ILP) of a clock placement problem for the circuit design from the clock properties and the physical clock region attributes. The ILP formulation can be solved to determine whether a feasible clock placement exists for the circuit design.

REFERENCES:
patent: 5555188 (1996-09-01), Chakradhar
patent: 7017043 (2006-03-01), Potkonjak
patent: 7207024 (2007-04-01), Scheffer
patent: 2007/0204252 (2007-08-01), Furnish et al.
U.S. Appl. No. 11/135,980, filed May 24, 2005, Slonim et al.

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