Static information storage and retrieval – Read/write circuit
Patent
1994-09-02
1995-12-05
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
365218, 365233, G11C 700
Patent
active
054735653
ABSTRACT:
The present invention provides a semiconductor memory circuit which can restrict the increase of an operation current in a flash write mode to a minimum even when there are problems caused in the manufacturing process such as short-circuits in the wiring. A timing control circuit of the semiconductor memory circuit of the present invention comprises an FW latch signal generation circuit and a latch circuit both for detecting that a row address strobe signal, an RAS signal and a flash write enable signal inputted have become active, and an FW gate signal generation circuit for activating the FW gate signal for only a limited fixed time determined by a delay circuit when an FW gate activation signal is outputted from the latch circuit which has detected the activation of both signals. With the FW gate signal activated, the flash write gate switch turns active for performing the flash write activity. After the flash write activity is finished, the FW gate signal becomes inactive immediately even when the RAS signal is active.
REFERENCES:
patent: 5003510 (1991-03-01), Kamisaki
patent: 5255243 (1993-10-01), Kitazawa
NEC Corporation
Popek Joseph A.
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