Method of finding critical nets in an integrated circuit design

Details Method of finding critical nets in an integrated circuit design Method of finding critical nets in an integrated circuit design

2006-09-12

2006-09-12

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07107558

ABSTRACT:
A method and computer program product for finding timing critical nets in an integrated circuit design includes steps of: (a) receiving an integrated circuit design as input; (b) calculating an approximate delay for each net in the integrated circuit design wherein the approximate delay includes an estimate of crosstalk delay; (c) identifying timing critical nets from the calculated delay for each net in the integrated circuit design; (d) calculating a corresponding exact delay for each of the timing critical nets; (e) replacing the approximate delay calculated for each of the timing critical nets with the corresponding exact delay to generate a corrected set of net delays for the integrated circuit design; and (f) generating as output the corrected set of net delays for the integrated circuit design.

REFERENCES:
patent: 6018623 (2000-01-01), Chang et al.
patent: 6378109 (2002-04-01), Young et al.
patent: 6405348 (2002-06-01), Fallah-Tehrani et al.
patent: 6907586 (2005-06-01), Al-Dabagh et al.
patent: 6907590 (2005-06-01), Al-Dabagh et al.
patent: 2004/0103386 (2004-05-01), Becer et al.

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