Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2008-03-25
2008-03-25
Toledo, Fernando L. (Department: 2823)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S623000, C438S624000, C438S761000, C438S780000, C257SE21579, C257SE21576, C257SE21581
Reexamination Certificate
active
07348281
ABSTRACT:
A method of forming via-first, dual damascene interconnect structures by using a gap-filling, bottom anti-reflective coating material whose thickness is easily controlled by a solvent is provided. After application to a substrate, the bottom anti-reflective coating is partially cured by baking at a low temperature. Next, a solvent is dispensed over the coated wafer and allowed to contact the coating for a period of time. The solvent removes the bottom anti-reflective coating at a rate controlled by the bottom anti-reflective coating's bake temperature and the solvent contact time to yield a bottom anti-reflective coating thickness that is thin, while maintaining optimum light-absorbing properties on the dielectric stack. In another possible application of this method, sufficient bottom anti-reflective coating may be removed to only partially fill the vias in order to protect the bottoms of the vias during subsequent processing. The solvent is removed from the wafer, and the bottom anti-reflective coating is cured completely by a high-temperature bake. The wafer is then coated with photoresist, and the trench pattern exposed. The bottom anti-reflective coating material used maintains a greater planar topography for trench patterning, eliminates the need for an inorganic light-absorbing material layer on the top of the dielectric stack, protects the bottom of the vias during the trench etch, and prevents the formation of fencing problems by using a solvent to control the thickness in the vias.
REFERENCES:
patent: 5091047 (1992-02-01), Cleeves et al.
patent: 5476816 (1995-12-01), Mautz et al.
patent: 5827781 (1998-10-01), Skrovan et al.
patent: 6015520 (2000-01-01), Appelt et al.
patent: 6020269 (2000-02-01), Wang et al.
patent: 6127070 (2000-10-01), Yang et al.
patent: 6156658 (2000-12-01), Wang et al.
patent: 6165695 (2000-12-01), Yang et al.
patent: 6171763 (2001-01-01), Wang et al.
patent: 6197678 (2001-03-01), Yu
patent: 6200907 (2001-03-01), Wang et al.
patent: 6225240 (2001-05-01), You et al.
patent: 6306560 (2001-10-01), Wang et al.
patent: 6309926 (2001-10-01), Bell et al.
patent: 6323123 (2001-11-01), Liu et al.
patent: 6407009 (2002-06-01), You et al.
patent: 6440640 (2002-08-01), Yang et al.
patent: 6455416 (2002-09-01), Subramanian et al.
patent: 6458705 (2002-10-01), Hung et al.
patent: 6477031 (2002-11-01), Hayashi
patent: 6509137 (2003-01-01), Wang et al.
patent: 6606793 (2003-08-01), Dunn
patent: 6638853 (2003-10-01), Sue et al.
patent: 2002/0016073 (2002-02-01), Kondo et al.
patent: 2002/0074659 (2002-06-01), Dalton et al.
patent: 2002/0110665 (2002-08-01), Rutter et al.
patent: 2003/0040179 (2003-02-01), Thakar et al.
patent: 2003/0054616 (2003-03-01), Endisch et al.
patent: 2004/0147108 (2004-07-01), Lamb, III et al.
patent: 2004/0183203 (2004-09-01), Meagley et al.
Aoi, Nobuo, et al., “A Novel Clustered Hard Mask Technology for Dual Damascene Multilevel Interconnects with Self-Aligned Via Formation Using an Organic Low k Dielectric,”1999 Symposium on VLSI Technology Digest of Technical Papers, 1999.
Brakensiek, Nick, “Bottom Anti-Reflective Coating Processing Techniques for Via-First Dual Damascene Processes,”Proceedings of SPIE, vol. 4691, 2002, pp. 927-936.
Ho, Paul, et al., “Challenges of damascene etching for copper interconnect,”Proceedings of SPIE, vol. 3883, 1999, pp. 34-41.
Brakensiek Nickolas L.
Murphy Earnest C.
Washburn Carlton A.
Brewer Science Inc.
Hovey & Williams, LLP
Jefferson Quovaunda
Toledo Fernando L.
LandOfFree
Method of filling structures for forming via-first dual... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of filling structures for forming via-first dual..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of filling structures for forming via-first dual... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2795525