Method of filling gaps on a semiconductor wafer

Details Method of filling gaps on a semiconductor wafer Method of filling gaps on a semiconductor wafer

2001-09-17

2003-05-13

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S789000, C438S792000, C438S424000

Reexamination Certificate

active

06562734

ABSTRACT:

BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a method of filling gaps on a semiconductor wafer with a dielectric material using a CVD (chemical vapor deposition) processing apparatus for performing a CVD-process under plasma and vacuum conditions at elevated temperatures.
When manufacturing integrated semiconductor circuits, certain process technologies require the filling of gaps on the surface of the semiconductor wafer. The wafer incorporates a plurality of integrated circuit elements after certain processing steps are executed. The requirement to fill gaps applies especially when manufacturing integrated circuit elements on semiconductor wafers that have been produced in accordance with sub 0.25 micron layout rules. The gaps may be located between transistors for isolation purposes according to the shallow trench isolation technique (STI) or may be located between polysilicon signal wires that precede the metalization process steps (premetal dielectric, PMD). The dielectric material to fill the gaps may be any known dielectric material as for example SiO
2
, BPSG, PSG, BSG, SiN, etc.
In known processes for the manufacturing of ICs rather complex or ineffective CVD-deposition processes for filling gaps were used. For example a High Density Plasma-(HDP)-CVD-reactor based on a silane/argon gas mixture at around 350 to 400° C. is used employing simultaneous oxide deposition and sputtering. Also, a HDP-CVD-process based on a silane-helium mixture at 600° C. is used for gap filling. However, helium is a very light ion and its sputter efficiency is almost zero. This leads to a bottom up fill of the gap.
Another process uses post deposition reflow, e.g. deposition of a glass on basis of boron phosphorous silane (BPSG) or tetra ethyl ortho silicate (TEOS) and a subsequent annealing at 850° C. Further, another process uses in situ reflow above the glass transition temperature which is greater than 750° C., e.g. in a Low Pressure-(LP)-CVD-reactor; the glass itself flows. Below the glass transition temperature at about 400 to 600° C. a Sub Atmospheric Pressure-(SA)-CVD-reactor is used. A SACVD reactor commonly operates at pressures in the range from 2.66×10
3
Pa to 8.0×10
4
Pa (20 to 600 Torr).
HDP-CVD-reactors operate at a very low pressure, typically in the range of 0.133 Pa to 3.33 Pa (1 to 25 mTorr). The reaction chamber is rather expensive. SACVD-reactors use aggressive ozone molecules. The turnaround time for wafers is rather low so that a number of SACVD-reactors have to be operated in parallel. Thus, HDP-CVD-based processes or SACVD-based processes are quite expensive.
U.S. Pat. No. 5,643,640 discloses a fluorine doped phosphosilicate glass process (FPSG) using a Plasma Enhanced-(PE)-CVD-deposition for filling gaps or voids. The gaps may have a high aspect ratio. The process is carried out at a temperature between 400 to 500° C. Using fluorine, however, has the drawback that the gate oxide may be contaminated, damaged or the fluorine may further be oxidized. Fluorine doped deposition materials are not desired in the lower front end of line levels of subquarter micron process technology.
U.S. Pat. No. 5,204,138 discloses a plasma enhanced CVD process for fluorinated silicon nitride films. The process runs at about 267 Pa to 1.33×10
3
Pa (2 to 10 Torr) at a temperature between 300° to 600° C. The fluorinated nitride film shows a high conformality over silicon trench structures.
International Publication No. WO 97/24761 discloses a void-free trench-fill process, which fills a trench in a two-step approach. The first step involves the deposition of a protection layer of silicon dioxide over the wafer into the trench. The second step involves forming a trench-fill layer of silicon dioxide over the protection layer. The two steps employ different RF bias levels to the wafer. During trench-fill the temperature of the wafer is kept in a range of about 200° to about 700° C.
In U.S. Pat. No. 5,356,722 the RF power for a PECVD TEOS deposition can be employed at a frequency of 13.56 MHz or at lower frequencies in the range between 100 to 450 kHz.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method of filling gaps on a semiconductor wafer which overcomes the above-mentioned disadvantages of the heretofore-known methods of this general type and which provides a good void-free filling of a gap with a dielectric material at moderate costs.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of filling gaps on a semiconductor wafer with a dielectric material, the method including the steps of:
inserting a semiconductor wafer into a reaction chamber of a plasma enhanced chemical vapor deposition processing apparatus;
providing a reaction gas including nitrogen and being free of an element selected from the group consisting of a halogen component and ozone;
performing a chemical vapor deposition (CVD) under plasma conditions and under vacuum conditions to deposit a dielectric material on the semiconductor wafer by using the reaction gas;
performing the chemical vapor deposition at a temperature above 500° C.; and
providing a reaction gas pressure between 13.3 Pa and 1.33×10
3
Pa (100 mTorr to 10 Torr) in the reaction chamber of the plasma enhanced chemical vapor deposition processing apparatus.
In other words, the method of the invention uses a plasma enhanced-(PE)-CVD-deposition apparatus at an elevated temperature above 500° C. Particularly the temperature is in the range of 500 to 700° C. In such a PECVD-process there is no need for using halogen ions or radicals. The PECVD-deposition process according to the invention is applicable to any common dielectric material, e.g. SiO
2
, BPSG, PSG, BSG, SiN, and provides a conformal filling of the gap. A PECVD-reaction chamber operates at reasonable temperatures and vacuum pressures so that the costs of the reactor are below that of a HDP-CVD-apparatus. The throughput of a PECVD-reactor is higher than for a SACVD-reactor. Practically, a PECVD-chamber according to the invention will cost approximately half of a HDP-CVD-chamber and will have approximately double the throughput of a SACVD-chamber.
The reaction temperature, which lies preferably between 500 and 700° C. is caused by a ceramic heating element located under the receptor carrying the semiconductor wafer. The vacuum is generated by a vacuum pump. The pressure is between 13.3 Pa and 1.33×10
3
Pa (100 mTorr and 10 Torr).
The plasma gas in the chamber is generated by a radio frequency signal. The signal has a frequency of more than 10 MHz, preferably 13.5 MHz. The radio frequency signal is coupled into the chamber opposite the front side of the wafer. According to a preferred embodiment of the invention a second radio frequency signal is coupled into the chamber, too. The second radio frequency signal has a frequency of less than 100 kHz, preferably about 10 kHz. This means that the two frequencies of the radio frequency signals differ by at least two orders of magnitude. The first radio frequency signal has a power of several hundreds of Watts. The second radio frequency signal is applied with lower power. Both signals are applied through different coupling devices into the chamber or through the same coupling devices.
The reaction gas composition in the chamber may be of any known type. Due to the high temperature an addition of halogen components or radical components as is ozone will not be necessary. The reaction gas or precursor gas composition includes one of the following compositions:
Dielectric Material to be Deposited—Precursor
SiO
2
—TEOS, O
2
, N
2
or SiH
4
, N
2
O, N
2
SiN—SiH
4
, N
2
O, NH
3
, N
2
BSG—TEOS, TEB, O
2
, N
2
or SiH
4
, B
2
H
6
, N
2
O, N
2
PSG—TEOS, TEPO, O
2
, N
2
or SiH
4
, PH
3
, N
2
O, N
2
BPSG—TEOS, TEB, TEPO, O
2
, N
2
or SiH
4
, PH
3
, B
2
H
6
, N
2
O, N
2
BSG/PSG/BPSG: Boro-/phosphorsilicate-/borophosphorsilicate-glass
TEB: Tri ethyl borate
TEPO: Tri ethyl phosphate
The semiconductor wafers to

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