Method of field isolation in silicon-on-insulator technology

Details Method of field isolation in silicon-on-insulator technology Method of field isolation in silicon-on-insulator technology

1999-10-01

2001-10-09

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S303000, C438S295000, C438S404000, C438S311000

Reexamination Certificate

active

06300172

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to methods of forming a transistor device with field isolation, or shallow trench isolation regions (STI), and specifically to forming a transistor device with shallow trench isolation regions in silicon-on-insulator (SOI) technology.
BACKGROUND OF THE INVENTION
Corner effects in current shallow trench isolation regions (STI) architecture leads to undesirable high leakage current and gate oxide isolation (GOI) issues.
U.S. Pat. No. 5,539,229 to Nobel, Jr. et al. describes a semiconductor structure comprising a transistor having a gate conductor that has first and second edges bounded by raised isolation structures, e.g. STI. A source diffusion is self-aligned to the third edge and a drain diffusion is self-aligned to the fourth edge of the gate electrode.
U.S. Pat. No. 5,610,083 to Chan et al. describes a process for creating a back gate contact in an SOI layer that can be incorporated into a MOSFET fabrication recipe. The back gate consists of an etched trench lined with insulator and filled with doped polysilicon. The polysilicon filled trench electrically connects the semiconductor substrate to overlying metal contacts.
U.S. Pat. No. 5,525,533 to Woodruff et al. describes a low voltage coefficient MOS capacitor, and a method of making such a capacitor, having substantially uniform parasitic effects over an operating voltage range and a low voltage coefficient. The capacitor comprises a first conductive layer superjacent a silicon-on-insulator substrate. The first conductive layer comprises heavily doped silicon having a first conductivity type while the substrate comprises a second conductivity type. The conductor further comprises an isolation trench surrounding the first conductive layer filled with a dielectric material. Positioned superjacent the first conductive layer is a dielectric layer thereby forming a dielectric shell on all sides of the first conductive layer except for its upper face. A second conductive layer is positioned superjacent the dielectric layer to form a low voltage coefficient capacitor.
U.S. Pat. No. 5,892,707 to Noble describes a memory array including a semiconductor substrate, an isolation trench disposed in the substrate, and a conductor that is disposed in the trench. The array also includes a memory cell that is coupled to the conductor in the trench. The conductor may be a digit line that is coupled to a source/drain of the memory cell or to a shared source/drain region of a pair of adjacent memory cells.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of forming shallow trench isolation regions in silicon-on-insulator technology reducing corner effects.
Another object of the present invention is to provide a method of forming shallow trench isolation regions in silicon-on-insulator technology reducing corner effects leading to leakage current and gate oxide isolation issues.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a silicon semiconductor structure is provided. A silicon oxide layer is formed over the silicon semiconductor structure. A silicon-on-insulator layer is formed over the oxide layer. A well is implanted in the silicon-on-insulator layer. A gate oxide layer is grown over the silicon-on-insulator layer. A polysilicon layer is deposited over the gate oxide layer. The polysilicon layer, gate oxide layer, and silicon oxide layer are patterned and etched to form trenches. The trenches are filled with an isolation material to at least a level even with a top surface of the polysilicon layer to form raised shallow trench isolation regions (STIs). The polysilicon layer is patterned and the non-gate portions are removed polysilicon adjacent the raised STIs forming a gate conductor between the raised STIs with the gate conductor and said raised STIs having exposed sidewalls. The gate oxide layer is removed between the gate conductor and the raised STIs, and outboard of the raised STIs. The source and drain are formed in the silicon-on-insulator layer adjacent the gate spacers. Silicide regions may then be formed on the source and drain.


REFERENCES:
patent: 5525533 (1996-06-01), Woodruff et al.
patent: 5539229 (1996-07-01), Noble, Jr. et al.
patent: 5610083 (1997-03-01), Chan et al.
patent: 5892707 (1999-04-01), Noble
patent: 5950090 (1999-09-01), Chen et al.
patent: 6110787 (1999-09-01), Chan et al.

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