Method of failure analysis with CAD layout navigation and FIB/SE

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H01J 3700

Patent

active

055612938

ABSTRACT:
A method of analyzing a failure of a sample, such as a wafer or a package unit made from a die sliced from the wafer, uses a computer aided design (CAD) tool in conjunction with a dual beam scanner and reverse engineering to improve the yield of the product. The computer aided design tool provides navigation to a location of interest over a layout of a wafer sample which has failed a test. The location of interest of the sample is then inspected using the dual beam scanner. The inspection may be made with either a focused ion beam scan or with a scanning electron microscope scan to provide different types of scan images and information. After inspection, a reverse engineering process (stripping back) is performed on the sample and the sample is inspected again to determine the cause of the failure of the sample. Once the cause of the failure is determined, the manufacturing process can be changed to improve the yield of the wafers.

REFERENCES:
patent: 5214283 (1993-05-01), Le

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