Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2011-08-30
2011-08-30
Trimmings, John (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S002000, C714S006240, C714S052000, C714S701000, C714S746000, C714S755000, C714S758000, C714S774000, C714S807000, C365S185090
Reexamination Certificate
active
08010876
ABSTRACT:
A method of facilitating reliably accessing flash memory is provided. During the write-in process, the present invention utilizes the steps of coding write-in data to generate extra data, and then generating the first error correction code by performing an error-correcting operation on the write-in data and the extra data. Finally, store the N write-in data and the generated K extra data into the data area and the first ECC into the spare area. During read process, the present invention utilizes the steps of reading data from the data area of the target flash-memory page to generate the second ECC, counting with the counter a number of bit differences between the first ECC and the second ECC, and selecting M data from the N write-in data and the K extra data as decoding factors to retrieve the N write-in data. The higher the counter values, the lower the likelihood the corresponding bit is selected to be retrieved.
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Hsieh Hsiang-chi
Hsieh Jen-wei
Kuo Tei-wei
Genesys Logic, Inc.
Kirton & McConkie
Trimmings John
Witt Evan R.
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