Method of fabricating well

Details Method of fabricating well Method of fabricating well

1998-07-28

2001-10-02

Wilczewski, Mary (Department: 2822)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ion implantation of dopant into semiconductor region

C438S224000, C438S228000

Reexamination Certificate

active

06297133

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 87108047, filed May 25, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of fabricating semiconductors, and more particularly to a method of fabricating wells.
2. Description of Related Art
The application of the data treatment at present is similar to the typical utilization in microprocessor and digital signal processor, which combine memory cell arrays and high-speed logic circuits on the same chip. For example, a high speed is used to store data into an integrated circuit device, such as a logic circuit, which has a DRAM cell array. This embedded DRAM has large benefits for the integrated circuit, which includes a logic circuit capable of processing large amount of data, such as graphic processor. For the process to combine the high-speed logic circuit and embedded DRAM on the same chip, it is necessary to form the logic circuit and memory cell on the chip.
For the conventional embedded DRAM of the integrated circuit, both the MOS transistor which is used for the DRAM and the MOS transistor which is used for the logic device are formed on the same chip. It has several advantages, such as improvement of the yield, and reducing of cycle time and manufacturing cost.
FIG. 1A
to
FIG. 1D
are cross-sectional views showing a conventional process of fabricating wells. Referring to
FIG. 1A
, a substrate
10
is provided. The substrate
10
is doped with p-type ions, that is a p-type substrate, is provided, the dosage of p-type ions is about 5E16/cm
3
. Then, a mask
12
is formed to cover part of the substrate
10
and expose another part of the substrate
10
. Thereafter, an n-well
14
is formed in the exposed substrate
10
by doping n-type ions, which have a dosage of about 1E17/cm
3
, into the exposed substrate
10
.
Referring to
FIG. 1B
, the mask
12
is removed after the n-well
14
is formed. Then, a mask
16
is formed to cover the surface of the n-well
14
and expose another part of the substrate
10
. Thereafter, a p-well
18
is formed in the exposed substrate
10
by doping p-type ions which have a dosage of about 1E17/cm
3
into the exposed substrate
10
.
Referring to
FIG. 1C
, the mask
16
is removed after the p-well
18
is formed. A mask
20
is formed to cover substrate
10
and partially expose the surface of the n-well
14
. Then, a p-well
22
, which is a triple well, is formed by doping p-type ions, which have a dosage of about 3E17/cm
3
, into the exposed part of the n-well
14
. P-well
22
is formed in the n-well
14
and the p-well
22
is shallow than the n-well
14
. That is, three surfaces of the p-well
22
are surrounded by the n-well
14
and one surface of the p-well
22
is exposed.
Referring to
FIG. 1D
, the mask
20
is removed after the p-well
22
is formed. Then the follow-up process is performed to complete the manufacture of the DRAM above the n-well
14
and the n-channel device above p-well
18
. The DRAM and n-channel device are not shown to simplify the figures.
In the conventional method as described above, it is necessary to implant high dosage p-type ions into the n-well
14
to form the triple well. Therefore, the dosage of the triple well is higher than that of the n-well
14
. When the DRAM is completed in subsequent processes, the DRAM's refresh time is shortened.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a method of manufacturing wells. This method can be used to shorten the refresh time of the DRAM.
In accordance with the foregoing and other objectives of the present invention, the method of manufacturing wells comprises the step of providing a p-type substrate and then sequentially forming a p-well and n-well with low dosage in the p-type substrate, respectively. Thereafter, energy is used to dope n-type ions into the p-well.


REFERENCES:
patent: 5108944 (1992-04-01), Shirai
patent: 5536665 (1996-07-01), Komori
patent: 5679588 (1997-10-01), Choi
patent: 5858812 (1999-01-01), Furumiya
patent: 5861330 (1999-01-01), Baker
patent: 5867425 (1999-02-01), Wong
patent: 5895251 (1999-04-01), Kim
patent: 6037203 (2000-03-01), Kim
patent: 6127710 (2000-10-01), Choi

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