Method of fabricating vias

Details Method of fabricating vias Method of fabricating vias

1999-04-12

2002-08-27

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S627000, C438S653000, C438S646000, C438S913000, C438S688000

Reexamination Certificate

active

06440841

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of fabricating an integrated circuit, and particularly to a method of fabricating a multilevel interconnect.
2. Description of the Related Art
In integration circuit process for semiconductor devices, the interconnects are provided between two devices for allowing electrical connection between different devices or components. Aluminum is one conducting material that has been widely used to fabricating vias. The main reasons for the pervasiveness of aluminum are its low resistivity and its good adhesion to silicon oxides and silicon.
Referring to
FIG. 1A
, in the conventional process for manufacturing vias using aluminum, a wetting layer
18
formed of titanium is deposited in the via opening
16
. An aluminum layer
20
is deposited by a sputtering process to fill the via opening
16
. The wetting layers
18
and the aluminum layer
20
left in the via opening
16
form a via plug. The wetting layer
18
and the aluminum layer
20
on the dielectric layer
14
are patterned by photolithography process and an etch process, as shown in FIG.
1
B.
In the above conventional process, the aluminum layer
20
formed by a sputtering process reacts with the titanium wetting layer
18
to form byproduct AlTi
3
during the aluminum deposition step. Therefore, the step coverage of the aluminum layer
20
is affected and becomes poor. The via-filling process suffers from the poor step coverage, and voids
30
are formed in the via plug consequently. This affects the device reliability. In addition, the vias formed of aluminum further suffers an electromigration problem. More specifically, an annealing step is performed after the sputter deposition of aluminum, so that the aluminum is usually in poly-crystalline state. The aluminum atoms move along the grain boundary in an electric field, and the movement results in an open-circuit failure. This also affects device reliability.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating interconnects. A semiconductor substrate having a dielectric layer is provided. The dielectric layer has at least a via opening, and the via opening expose a part of the semiconductor substrate. A titanium layer is formed along a surface profile of the via opening. The surface of the titanium layer is covered with an Al—Si—Cu alloy layer formed by a sputtering process at a substantially low temperature. The via openings are filled with an Al—Cu alloy layer formed by a sputtering process at a substantially high temperature, such that the Al—Cu alloy covers the surface of the Al—Si—Cu alloy layer.
In one preferred embodiment of the method of the present invention, the Al—Si—Cu alloy layer is formed at a temperature of about 0° C. to about 200° C. The composition of the Al—Si—Cu alloy layer has a silicon weight percentage of about 0.5% to about 1% and a copper weight percentage of about 0.4% to about 0.6%. The Al—Cu alloy layer is formed at a temperature from about 380° C. to about 450° C. The composition of the Al—Cu alloy layer has a copper weight percentage of about 0.4% to about 0.6%. The Al—Si—Cu alloy layer and the Al—Cu alloy layer comprise copper, so that the electromigration can be inhibited. The Al—Si—Cu alloy layer formed at a low temperature comprises silicon, so that the formation of the byproduct AlTi
3
from the reaction of aluminum and titanium can be suppressed. Because the byproduct is suppressed from being formed, the Al—Si—Cu alloy layer thus inheres continuity which results in a good step coverage. In addition, the Al—Cu alloy layer is formed at a high temperature, which prevents the precipitation of silicon during the sputtering step of the Al—Cu alloy layer and avoids a silicon nodule after a metal etching step in the following process. The Al—Si—Cu alloy layer is between the Al—Cu alloy layer and the titanium layer, so that aluminum of the Al—Cu alloy layer does not react with titanium to produce AlTi
3
byproducts. Thus, the step coverage of the Al—Cu alloy layer is not affected, and the filling problem can be suppressed. Therefore, the method of the present invention can be used to improve the step coverage and to avoid forming voids in the vias, so that the reliability of devices can be increased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5356836 (1994-10-01), Chen et al.
patent: 5523259 (1996-06-01), Merchant et al.
patent: 5543357 (1996-08-01), Yamada et al.
patent: 5677238 (1997-10-01), Gn et al.
patent: 5804251 (1998-09-01), Yu et al.
patent: 5904562 (1999-05-01), Nulman
patent: 6107182 (2000-08-01), Asahina et al.

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