Method of fabricating vertical epitaxial SOI transistor

Details Method of fabricating vertical epitaxial SOI transistor Method of fabricating vertical epitaxial SOI transistor

1994-12-22

1997-06-24

Bowers, Jr., Charles L.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

438242, 438489, H01L 21205, H01L 218242

Patent

active

056416946

ABSTRACT:
Vertical epitaxial SOI transistors and memory cells are disclosed. The devices are formed completely within a substrate trench and have a bulk channel epitaxially grown on an exposed surface of the substrate within the trench. The bulk channel is disposed proximate to a transistor gate electrode such that an inversion layer is formed therein when the gate electrode is appropriately biased. Back biasing of the bulk region is accomplished through the substrate. In the transistor embodiment, a first node diffusion and a second node diffusion are disposed at opposite ends of the bulk channel. In a memory cell configuration the access transistor is disposed above a trench storage node, which electrically connects with the transistor's second node diffusion. Arrays of the trench transistors and trench memory cells are also described. Further, fabrication methods for the various structures disclosed are presented. A novel wiring approach to construction of bit lines in a cell array is also set forth.

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