Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2011-06-07
2011-06-07
Smith, Bradley K (Department: 2894)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S620000, C438S622000, C438S637000, C257SE21249, C257SE21476
Reexamination Certificate
active
07955967
ABSTRACT:
A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.
REFERENCES:
patent: 5841195 (1998-11-01), Lin et al.
patent: 6133144 (2000-10-01), Tsai et al.
patent: 6180997 (2001-01-01), Lin
patent: 6232663 (2001-05-01), Taniguchi et al.
patent: 6727169 (2004-04-01), Raaijmakers et al.
patent: 6943067 (2005-09-01), Greenlaw
patent: 7102235 (2006-09-01), Raaijmakers et al.
patent: 7205224 (2007-04-01), Mandal
patent: 2002/0076916 (2002-06-01), Yamashita et al.
patent: 2002/0142235 (2002-10-01), Hamanaka et al.
patent: 2003/0129829 (2003-07-01), Greenlaw
patent: 2004/0130029 (2004-07-01), Raaijmakers et al.
patent: 2004/0232554 (2004-11-01), Hirano et al.
patent: 2004/0241984 (2004-12-01), Schwan et al.
patent: 2006/0240652 (2006-10-01), Mandal
patent: 2007/0152342 (2007-07-01), Tsao et al.
patent: 2008/0303169 (2008-12-01), Goller et al.
Notice of Allowance (Mail Date Jan. 13, 2010) for U.S. Appl. No. 11/853,118, filed Sep. 11, 2007; Confirmation No. 2505.
Office Action (Mail Date Jun. 19, 2009) for U.S. Appl. No. 11/853,139, filed Sep. 11, 2007; Confirmation No. 2541.
Office Action (Mail Date Jun. 25, 2009) for U.S. Appl. No. 11/853,118, filed Sep. 11, 2007; Confirmation No. 2505.
Notice of Allowance (Mail Date Dec. 14, 2009) for U.S. Appl. No. 11/853,139, filed Sep. 11, 2007; Confirmation No. 2541.
Office Action (Mail Date Dec. 27, 2010) for U.S. Appl. No. 12/540,490, filed Aug. 13, 2009; Confirmation No. 1427.
La Tulipe, Jr. Douglas C.
Robson Mark Todhunter
International Business Machines - Corporation
Payen Marvin
Percello Louis J.
Schmeiser Olsen & Watts
Smith Bradley K
LandOfFree
Method of fabricating ultra-deep vias and three-dimensional... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating ultra-deep vias and three-dimensional..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating ultra-deep vias and three-dimensional... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2741226