Method of fabricating transistor with silicon oxycarbide gate

Details Method of fabricating transistor with silicon oxycarbide gate Method of fabricating transistor with silicon oxycarbide gate

1998-08-21

2001-10-30

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Having diamond semiconductor component

C438S059000, C438S264000

Reexamination Certificate

active

06309907

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to integrated circuit technology, and particularly to a silicon oxycarbide gate transistor, such as a floating gate transistor, and complementary metal-oxide-semiconductor (CMOS) compatible methods of fabrication, and methods of use in memory and imaging devices.
BACKGROUND OF THE INVENTION
Field-effect transistors (FETs) are typically produced using a standard complementary metal-oxide-semiconductor (CMOS) integrated circuit fabrication process. Such a process allows a high degree of integration for obtaining a high circuit density with relatively few processing steps. Resulting FETs typically have gate electrodes composed of n-type conductively doped polycrystalline silicon (polysilicon).
The intrinsic properties of the polysilicon gate material affects operating characteristics of the FET. Silicon (monocrystalline and polycrystalline) has intrinsic properties that include a relatively small energy bandgap (E
g
), e.g. approximately 1.2 eV, and a corresponding electron affinity (&khgr;) that is relatively large, e.g. &khgr;≈4.2 eV. For example, for p-channel FETs fabricated by a typical CMOS process, these and other material properties result in a large turn-on threshold voltage (V
T
) magnitude. As a result, the V
T
magnitude must be downwardly adjusted by doping the channel region that underlies the gate electrode of the FET.
Another drawback with polysilicon gate FETs arises during use as a nonvolatile memory device, such as in electrically erasable and programmable read only memories (EEPROMs). EEPROM memory cells typically use FETs having an electrically isolated (floating) gate that affects conduction between source and drain regions of the FET. A gate dielectric is interposed between the floating gate and an underlying channel region between source and drain regions. A control gate is provided adjacent to the floating gate, separated therefrom by an intergate dielectric.
In such memory cells, data is represented by charge stored on the polysilicon floating gates. Fowler-Nordheim tunneling is one method that is used to store charge on the polysilicon floating gates during a write operation and to remove charge from the polysilicon floating gate during an erase operation. However, the relatively large electron affinity of the polysilicon floating gate presents a relatively large tunneling barrier energy at its interface with the underlying gate dielectric. The large tunneling barrier energy provides longer data retention times than realistically needed. For example, a data charge retention time at 85° C. is estimated to be in millions of years for some floating gate memory devices. The large tunneling barrier energy also increases the time needed to store charge on the polysilicon floating gates during the write operation and the time needed to remove charge from the polysilicon floating gate during the erase operation. This is particularly problematic for “flash” EEPROMs, which have an architecture that allows the simultaneous erasure of many floating gate transistor memory cells. Since more charge must be removed from the many floating gates in a flash EEPROM, even longer erasure times are needed to accomplish this simultaneous erasure. There is a need in the art to obtain floating gate transistors allowing faster storage and erasure, such as millisecond erasure periods for flash EEPROMs.
Other problems result from the large erasure voltages that are typically applied to a control gate of the floating gate transistor in order to remove charge from the floating gate. These loge erasure voltages are a consequence of the large tunneling barrier energy between the polysilicon floating gate and the underlying gate dielectric. The large erasure voltages can result in hole injection into the gate dielectric. This can cause erratic overerasure, damage to the gate dielectric, and introduction of trapping states in the gate dielectric. The high electric fields that result from the large erasure voltages can also result in reliability problems, leading to device failure. There is a need in the art to obtain floating gate transistors that allow the use of lower erasure voltages.
Halvis et al. (U.S. Pat. No. 5,369,040) discloses a charge-coupled device (CCD) photodetector which has transparent gate MOS imaging transistors fabricated from polysilicon with the addition of up to 50% carbon, and preferably about 10% carbon, which makes the gate material more transparent to the visible portion of the energy spectrum. The Halvis et al. patent is one example of a class of conventional CCD photodetectors that are directed to improving gate transmissivity to allow a greater portion of incident light in the visible spectrum to penetrate through the gate for absorption in the semiconductor substrate. However, the absorption of photons in the semiconductor substrate is limited to high energy photons exceeding a bandgap energy of the semiconductor substrate. There is a need in the art to detect lower energy photons independently of the semiconductor bandgap energy limitation. For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, the above described needs are unresolved in the art of fabrication of imaging devices, FETs, and EEPROMs using CMOS processes.
SUMMARY OF THE INVENTION
The present invention includes a transistor having a silicon oxycarbide (SiOC) gate. The transistor includes a source region, a drain region, and a channel region between the source and drain regions. A gate is separated from the channel region by an insulator. The gate is formed of a silicon oxycarbide compound SiO
(2-2w)
C
w
. The SiOC composition w is selected approximately between 0 and 1.0, such as to establish a desired value of a barrier energy between the gate and the insulator. In one embodiment, the gate is an electrically isolated floating gate and the transistor includes a control gate, separated from the floating gate by an intergate dielectric.
In another embodiment, the present invention includes an imaging device that is capable of detecting low energy photons independent of a semiconductor bandgap energy. The imaging device includes a source region, a drain region, and a channel region between the source and drain regions. A floating gate is separated from the channel region by an insulator. The floating gate is formed of a silicon oxycarbide compound SiO
(2-2w)
C
w
. The SiOC composition w is selected approximately between 0 and 1.0, such as to establish a desired value of a barrier energy between the gate and the insulator. The floating gate is adapted for emission of charge from the floating gate in response to absorbed incident photons.
In another embodiment, the present invention includes a memory device that is capable of providing short programming and erase times, low programming and erase voltages, and lower electric fields in the memory cell for improved reliability. The memory device includes a plurality of memory cells, each providing a transistor. Each transistor includes a source region, a drain region, and a channel region between the source and drain regions. A floating gate is separated from the channel region by an insulator. The floating gate is formed of a silicon oxycarbide compound SiO
(2-2w)
C
w
. The SiOC composition w is selected at a value approximately between 0 and 1.0, such as to establish a desired value of a barrier energy between the gate and the insulator. A control gate is located adjacent to the floating gate and separated therefrom by an interlayer dielectric.
In another embodiment, the present invention includes a method of producing a SiOC gate transistor on a semiconductor substrate. Source and drain regions are formed, thereby defining a channel region between the source and drain regions. An insulating layer is formed on the channel region. A gate is formed on the insulating layer. The gate comprises a silicon oxycarbide compound SiO
(2-2w)
C
w
. The SiOC composition w is se

Affiliated with

Also associated with

Rating

Method of fabricating transistor with silicon oxycarbide gate does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating transistor with silicon oxycarbide gate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating transistor with silicon oxycarbide gate will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2586000