Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-06-22
2003-08-12
Fahmy, Wael (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S152000, C438S155000, C438S158000, C438S160000
Reexamination Certificate
active
06605494
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a thin film transistor (TFT) of an active matrix liquid crystal display (LCD) and a related TFT structure. More particularly, the present invention is directed to a method of fabricating a TFT in which a semiconductor layer and ohmic contact layer are formed successively so as to prevent a native oxide layer from being formed therebetween, and in which the semiconductor layer, as well as source and drain electrodes, are patterned using a single mask in order to reduce the number of masking steps.
2. Discussion of Related Art
An active matrix LCD includes a matrix of pixels, each having a TFT switching element and associated pixel electrode electrically connected to the TFT. The TFT may have either a coplanar or staggered structure. The staggered type TFT utilizes amorphous silicon as its semiconductor layer and can therefore be manufactured at temperatures below 300° C., which is lower than the temperature required to fabricate a coplanar polysilicon TFT. Accordingly, the staggered TFT can be fabricated on an inexpensive glass substrate.
There are two types of staggered TFT's; reverse stagger type and regular stagger type TFTs. In the reverse stagger type TFT, the gate electrode is formed under the semiconductor layer; while the gate electrode of the regular stagger type TFT is formed on the semiconductor layer. The reverse stagger type TFT is widely used because the amorphous silicon is damaged less during the layer deposition step of the TFT fabricating process, and its electron mobility is relatively high.
There are two kinds of reverse stagger type TFTs as well; back channel etched (BCE) type and etch stopper (ES) type. During manufacture of the BCE type TFT, when a heavily doped amorphous silicon ohmic contact layer is removed using source and drain electrodes as a mask, the semiconductor layer may be damaged. On the other hand, the ES type TFT has an etch stop layer so that its ohmic contact layer can be easily removed without damaging the surface of the semiconductor layer.
FIGS. 1A
to
1
D are cross-sectional views showing a conventional process for fabricating an etch stopper type TFT. As shown in
FIG. 1A
, a metal is deposited on a transparent insulating substrate
11
through a sputtering method and patterned by conventional photolithography to form gate electrode
13
. The metal is preferably selected from the group of aluminum (Al), aluminum alloy, molybdenum (MO), molybdenum alloy, titanium (Ti), titanium alloy, tantalum (Ta), tantalum alloy, cobalt (Co) and cobalt alloy. Silicon oxide or silicon nitride is then deposited on the surface of the gate electrode
13
and substrate
11
in a single layer or a double layer of the two dielectrics, to form an insulating layer
15
.
Referring to FIG.
1
B. undoped amorphous silicon is deposited on insulating layer
15
to form a semiconductor layer
17
. Silicon oxide or silicon nitride is next deposited on semiconductor layer
17
to form an etch stop layer
19
, followed by a photoresist layer coating (not shown). Then, the photoresist is back-etched and developed using the gate electrode
13
as a mask, such that only a portion of the photoresist layer remains covering part of semiconductor layer
17
corresponding to gate electrode
13
. Thereafter, the etch stop layer
19
is selectively etched using the photoresist as a mask, thereby exposing a portion of the semiconductor layer
17
. The photoresist is then removed.
Referring to
FIG. 1C
, a heavily doped amorphous silicon layer is deposited on the semiconductor layer
17
and an etch stop layer
19
. The heavily doped amorphic silicon layer is patterned by photolithography to form ohmic contact layer
21
. Semiconductor layer
17
is also patterned in this photolithography step. A conductive metal, such as aluminum, is then deposited on insulating layer
15
and ohmic contact layer
21
, and patterned to form source and drain electrodes
23
and
25
, respectively. An exposed portion of the ohmic contact layer
21
is next etched using the source and drain electrodes
23
and
25
as a mask. Here, over-etching is carried out in order to prevent a portion of the ohmic contact layer from remaining on the etch stop layer
19
. Accordingly, the etch stop layer
19
prevents the surface of the semiconductor layer
17
from being damaged during the over-etching.
As seen in
FIG. 1D
, silicon oxide or silicon nitride is deposited on the substrate by chemical vapor deposition (CVD), to form a passivation layer
27
. Next, a portion of passivation layer
27
is selectively removed in order to form a contact hole
28
exposing a predetermined portion of the drain electrode. A transparent conductive material is then deposited on the passivation layer
27
and patterned to form a pixel electrode
29
, while electrically connected to drain electrode
25
through contact hole
28
.
In the conventional method of fabricating TFT described above, the source and drain electrodes are formed on a portion of the ohmic contact layer other than a portion corresponding to the gate electrode, and the ohmic contact layer is removed by an over-etching process using the source and drain electrodes as a mask. Thus, damage to the semiconductor layer is minimized. However, since the semiconductor layer and source and drain electrodes are respectively patterned using different masks, the number of masking steps is increased. Furthermore, the semiconductor layer and ohmic contact layer are not formed successively. Accordingly, an additional step is required to remove a native oxide layer formed between these two layers.
SUMMARY OF THE INVENTION
The present invention is directed to a method of fabricating a TFT that substantially obviates one or more of the problems caused by limitations and disadvantages of the conventional TFT fabrication process described above.
An object of the present invention is to provide a method of fabricating a TFT in which a semiconductor layer and ohmic contact layer are formed successively so that a native oxide layer does not form therebetween.
Another object of the present invention is to provide a method of fabricating a TFT in which a semiconductor layer and source and drain electrodes are patterned using a single mask so as to reduce the total number of mask steps required to fabricate the TFT.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof, as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the method of fabricating a thin film transistor, comprises the steps of forming a gate electrode on a predetermined portion of a transparent insulating substrate; forming an insulating layer on the substrate and gate electrode; forming a first semiconductor layer on a portion of the insulating layer corresponding to the gate electrode; successively forming a second semiconductor layer, a heavily doped first conductivity type ohmic contact layer and conductive metal layer on the insulating layer and first semiconductor layer; patterning the conductive metal layer to form source and drain electrodes; and removing an exposed portion of the ohmic contact layer and second semiconductor layer, thereby exposing a portion of the insulating layer and first semiconductor layer; forming a passivation layer on the insulating layer and first semiconductor layer, thereby covering the source and drain electrodes; forming a contact hole through the passivation layer in order to expose a predetermined portion of the drain electrode; and forming on the passivation layer a pixel electrode electrically connected to the drain electrode through
Kim Jung-Hoan
Lee Jae-Kyun
Park Jae-Yong
Fahmy Wael
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
LG Electronics Inc.
Rao Shrinivas H
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