Method of fabricating TFT with self-aligned structure

Details Method of fabricating TFT with self-aligned structure Method of fabricating TFT with self-aligned structure

2003-04-22

2004-10-12

Zarneke, David (Department: 2827)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S197000, C438S299000, C438S301000, C438S306000

Reexamination Certificate

active

06803263

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating thin film transistor (TFT), and more particularly, to a method of fabricating a TFT with self-aligned structure.
2. Description of the Related Art
Polysilicon thin film transistors (Poly-Si TFT) have been widely used in active matrix liquid crystal display (AMLCD) and static random access memory (SRAM) applications. One of the major problems of poly-Si TFTs is OFF-state leakage current, which causes charge loss in LCDs or high standby power dissipation in SRAMs. Seeking to solve this problem, conventional lightly doped drain (LDD) structures have been used to reduce the drain field, thereby reducing the leakage current. The conventional method of forming Poly-Si TFT with a LDD structure is shown with reference to FIGS.
1
A~
1
B.
Firstly, as shown in
FIG. 1A
, a transparent insulating substrate
10
is provided, with a semiconductor layer
12
formed on a predefined surface thereof, with a gate insulating layer
14
formed covering the semiconductor layer
12
.
Conventionally, a first mask process forms a patterned photoresist layer
16
on the gate insulating layer
14
, and the patterned photoresist
16
is used as a mask in a heavy ion implantation
17
creating a heavily doped region
18
in the semiconductor layer
12
, such that the heavily doped region
18
serves as a source/drain region.
Next, as shown in
FIG. 1B
, after removing the patterned photoresist
16
, a second mask process is performed on the gate insulating layer
14
to determine and form a gate layer
20
, the gate layer
20
covering only a part of the undoped regions of the semiconductor layer
12
to predefine the LDD position. Moreover, using gate layer
20
as a mask, a light ion implantation process
21
forms a lightly doped region
22
on the undoped region on both sides of the gate layer
20
in the semiconductor layer
12
. Thus, the lightly doped region
22
serves as the LDD structure and the region of the semiconductor layer
12
covered by the gate layer
20
serves as a channel region.
However, in the conventional method of determining the position of the LDD structure, an extra photomask process is required, thus errors in alignment are easily caused by resulting shifts in the LDD structure. Excessive shifts in LDD structure can seriously affect the electrical performance of the poly-TFT.
SUMMARY OF THE INVENTION
An object of the present invention is thus to provide a method of fabricating TFT with a self-aligned structure.
The present invention only employs one photomask step to define an exact position of the gate and the LDD, thereby reducing conventional process by one photomask step and avoiding alignment errors, further improving electrical performance of the poly-Si TFT.
In order to achieve these objects, the present invention provides a method of fabricating TFT with a self-aligned structure, comprising providing a substrate with a semiconductor layer and gate insulation layer formed thereon in sequence, followed by formation of a conductive layer on the gate insulation layer, and definition of the conductive layer to form a gate conductive layer and a dummy conductive layer. The dummy conductive layer is on both sides of the gate conductive layer and is provided with a gap therebetween. Next, a first ion implantation is performed via the gap to form a lightly doped region on the semiconductor layer thereunder, and a sacrificial layer is formed to fill the gap. The dummy conductive layer is then removed. The gate conductive layer and a part of the remaining sacrificial layer are used as a mask. Finally, a second ion implantation is performed to form a heavily doped source/drain region on the semiconductor layer.


REFERENCES:
patent: 6096642 (2000-08-01), Wu
patent: 6281077 (2001-08-01), Patelmo et al.
patent: 6331468 (2001-12-01), Aronowitz et al.
patent: 6566215 (2003-05-01), Chong et al.
patent: 2002/0132404 (2002-09-01), Chen et al.
patent: 2002/0158289 (2002-10-01), Kim

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