Method of fabricating T-type gate

Details Method of fabricating T-type gate Method of fabricating T-type gate

2006-11-28

2006-11-28

Estrada, Michelle (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C438S180000, C438S579000, C257S284000, C257S280000, C257S472000, C257SE33051, C257SE31074

Reexamination Certificate

active

07141464

ABSTRACT:
Provided is a method of fabricating a T-type gate including the steps of: forming a first photoresist layer, a blocking layer and a second photoresist layer to a predetermined thickness on a substrate, respectively; forming a body pattern of a T-type gate on the second photoresist layer and the blocking layer; exposing a predetermined portion of the second photoresist layer to form a head pattern of the T-type gate, and performing a heat treatment process to generate cross linking at a predetermined region of the second photoresist layer except for the head pattern of the T-type gate; performing an exposure process on an entire surface of the resultant structure, and then removing the exposed portion; and forming a metal layer of a predetermined thickness on an entire surface of the resultant structure, and then removing the first photoresist layer, the blocking layer, the predetermined region of the second photoresist layer in which the cross linking are generated, and the metal layer, whereby it is possible to readily perform a compound semiconductor device manufacturing process, and to reduce manufacturing cost by means of the increase of manufacturing yield and the simplification of manufacturing processes.

REFERENCES:
patent: 5776805 (1998-07-01), Kim
patent: 5930610 (1999-07-01), Lee
patent: 6524937 (2003-02-01), Cheng et al.
patent: 10 0261268 (2000-04-01), None
patent: 10 0274153 (2000-09-01), None
“T-Shape Gate Process & Its Application In HFET Fabrication” Zheng et al., Microelectronic R&D Center of Chinese Academy of Sciences, 2001 IEEE pp. 1334-1336.
“First demonstration of InA1As/InGaAs HEMTs using T-gates fabricated by a bilayer of UVIII and PMMA resists” Chen et al., Nanoelectronics Research Centre, Department of Electronics and Electrical Engineering, 2000 IEEE pp. 202-205.
“Single step lithography for double-recessed gate pseudomorphic high electron mobility transistors” Grundbacher et al., J. Vac. Sci. Technol. B 15(1), Jan./Feb. 1997 pp. 49-52.

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