Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-11-06
2002-11-12
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S155000, C257S347000
Reexamination Certificate
active
06479328
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a Silicon-On-Insulator (SOI) wafer, and more particularly to a method of fabricating a SOI wafer capable of providing good device characteristics.
2. Description of the Related Art
With the development of high integration and high performance semiconductor devices, a semiconductor integration technology using a SOI wafer instead of a single crystal Si wafer comprised of a bulk silicon has proven to be attractive. This is because the semiconductor device integrated in the SOI wafer offers advantages in high speed driving due to low junction capacitance, low voltage driving due to low threshold voltage and decreased latch-up due to more complete device isolation, when compared to single crystal Si wafer integrated technology.
The SOI wafer has a stack structure of a base substrate as supporting means, a buried oxide layer as a bonding medium disposed on the base substrate and a semiconductor layer for providing a device formation region which is disposed on the buried oxide layer. The two main methods of forming a SOI wafer are the implanted oxygen (SIMOX) method and the bonding method.
The SIMOX method fabricates a SOI wafer comprising a stack structure of a base substrate, a buried oxide layer and a semiconductor layer. The semiconductor layer is produced by implanting oxygen ions into a Si wafer at a selected depth from the surface of the Si wafer. During a subsequent heat treatment the implanted oxygen reacts with the Si to form a layer of silicon dioxide that separated the base substrate and the semiconductor layer.
The prior art bonding method fabricates a SOI wafer having a similar stack structure comprising a base substrate, a buried oxide layer and a semiconductor layer by bonding two Si substrates, for example, the base substrate and a semiconductor substrate with interleaving the oxide layer and polishing a partial thickness of the back face of the semiconductor substrate so as to form a semiconductor layer.
However, the SIMOX method, requiring both an ion implantation step and a subsequent heat treatment step, makes it difficult to control the thickness of the semiconductor layer and takes a relatively long time for process. Using the bonding method to fabricate a SOI wafer is relatively simple, but it is still difficult to obtain a semiconductor layer of a desired thickness because there is no polishing stopper layer available for use during the polishing process to form a consistent and uniform semiconductor layer.
Recently, a variation of the bonding method having a trench type isolation layer functioning as a polishing stopper during the CMP process on the semiconductor substrate. The planarized semiconductor substrate is then bonded to the base substrate to form a SOI wafer.
Hereinafter, a method of fabricating a SOI wafer according to the prior art will be described with reference to
FIGS. 1A and 1B
.
FIG. 1A
shows a semiconductor substrate
1
a
comprising bulk single crystal Si. A trench T is formed by etching a portion of the semiconductor substrate
1
a.
A trench type isolation layer
2
that will serve as a polishing stopper layer is formed by filling the trench T with an oxide layer. At this time, the trench T is formed having a slope of 83~85° to provide a top rounding effect for restraining formation of the characteristic hump topography and a bottom rounding effect for improving junction leakage current, thereby obtaining improved device characteristics. A first oxide layer
3
a
is formed on the isolation layer
2
and the semiconductor substrate
1
a.
Referring to
FIG. 1B
, a base substrate
4
is prepared and a second oxide layer
3
b
is formed on the base substrate
4
. The base substrate
4
and the semiconductor substrate
1
are bonded to contact the first oxide layer
3
a
with the second oxide layer
3
b.
A semiconductor layer
1
a
is formed by polishing the semiconductor substrate with a Chemical Mechanical Polishing (hereinafter, CMP) process using the isolation layer
2
as the polishing stopper, thereby forming a SOI wafer having a stack structure of the base substrate
1
, a buried oxide layer
3
comprising the first and second oxide layers
3
a
and
3
b,
and the semiconductor layer having the isolation layer
2
.
However, the method of fabricating the SOI wafer according to the prior art is incapable of obtaining the most desirable device characteristics for the following reasons.
First, when forming the isolation layer
2
, the trench T has the slope of 83~85° to secure good device characteristics. However, the trench T is incapable of obtaining the good device characteristic since the upper and lower portions thereof are reversed during subsequent processing.
Second, the characteristics of devices integrated in the SOI wafer largely depend on the thickness uniformity of the semiconductor layer
1
a.
The polishing of the semiconductor substrate using the isolation layer as the polishing stopper, as shown in
FIG. 1B
, generates a dishing D on the surface of the semiconductor layer. This dishing is due to the difference in polishing removal rates between the Si and the oxide layers which can be characterized by a selectivity ratio, thereby degrading the thickness uniformity of the semiconductor layer
1
a.
Consequently, good device characteristics can not be obtained.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of fabricating a SOI wafer capable of providing improved device characteristics.
To accomplish the above-mentioned object, the present invention provides a method of fabricating a SOI wafer, comprising: preparing a semiconductor substrate and a base substrate; forming a pad oxide layer, a nitride layer, and a mask oxide layer in sequence on one surface of the semiconductor substrate; etching the pad oxide layer, the nitride layer and the mask oxide layer to expose an isolation region of the semiconductor substrate; etching the exposed semiconductor substrate region to form a trench; removing the mask oxide layer; field-oxidizing the low surface of the trench to form a field oxide layer having bird's-beak at the edge thereof; removing the field oxide layer; burying the oxide layer into the trench to form a trench type isolation layer; removing the nitride layer and the pad oxide layer; depositing a first insulating layer on the isolation layer and the semiconductor substrate; depositing a second insulating layer on the base substrate; bonding the semiconductor substrate and the base substrate to contact the first insulating layer with the second insulating layer; initially polishing the surface of the semiconductor substrate using the isolation layer as a polishing stopper; and subsequently polishing surface of the semiconductor substrate to form a semiconductor layer of a desired thickness.
REFERENCES:
patent: 5416041 (1995-05-01), Schwalke
patent: 6207532 (2001-03-01), Lin et al.
Coleman William David
Fahmy Wael
Hyundai Electronics Industries Co,. Ltd.
LandOfFree
Method of fabricating SOI wafer does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating SOI wafer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating SOI wafer will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2971276