Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1999-02-16
2001-02-20
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S788000
Reexamination Certificate
active
06191004
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of fabricating an isolation region in a semiconductor substrate.
2. Description of the Related Art
In the semiconductor fabrication process, shallow trench isolations (STI) are frequently used. A shallow trench isolation is formed in an integrated circuit for the purpose of separating neighboring device regions of a semiconductor substrate and preventing the carriers from penetrating through the substrate to neighboring devices. The shallow trench isolation is commonly formed by anisotropically etching to form a trench in the substrate, and depositing an isolation layer in the trench to form an isolation region.
In the above procedure of depositing the isolation layer in the trench, the conventional method uses atmospheric-pressure chemical vapor deposition (APCVD), sub-atmospheric pressure chemical vapor deposition (SACVD), or high-density plasma chemical vapor deposition (HDPCVD) to deposit the isolation layer.
In contrast with the conventional chemical vapor deposition, the HDPCVD step is performed with a lower temperature to form an isolation layer with a high quality. In addition, the isolation layer formed by HDPCVD has a high densification, a high moisture isolation, and a high planarization. Thus, the HDPCVD step of forming the isolation layer into the trench is advantageous to the process for forming a shallow trench isolation.
During the performance of conventional HDPCVD, argon is provided together with oxygen plasma. A deposition step for forming an isolation layer, such as a silicon oxide layer, is performed with a SiH
4
source gas. Additionally, bias power is supplied during the deposition step. By supplying bias power, argon plasma is attracted to a chip surface and bombards the chip to form a silicon oxide layer. This process can provide a high-quality silicon oxide layer that has a high step coverage ability.
In
FIG. 1. a
trench
102
is formed in a substrate
100
. A HDPCVD step is performed to form a silicon oxide layer
104
that fills the trench
102
. Due to the bias power provided during the entire process of forming the silicon oxide layer
104
, the speed of the argon gas is increased to a high level, so that the silicon oxide layer
104
is formed with a good gap-filling ability. However, the argon gas supplied in this conventional method described above has a wide angle. This, in turn, forms clipped
106
on top of the trench
102
. Additionally, the high-speed argon gas easily damages the trench
102
. which leads to a formation of a damage region
108
.
Reference is now made to
FIG. 2
, which explains another conventional method of forming a shallow trench isolation. A HDPCVD is first performed without providing a bias power. A conformal liner oxide
204
, which is made of silicon oxide, is formed on a substrate
200
exposed in a trench
202
. A HDPCVD is then performed with bias power. A second silicon oxide layer is formed to fill the trench
202
. In the step of forming the liner oxide layer, the HDPCVD is performed without the bias power. In comparison with a process in which a bias power is provided, the speed of argon gas is lowered. In this manner, with a low speed of argon gas, a clipped corner
106
and a damage region
108
(shown in
FIG. 1
) can be avoided. Unfortunately, in the method described above, the liner oxide layer
204
easily forms overhang top corner
207
. Hence, in the step of forming a silicon oxide layer
206
, the overhang top corner
207
affects the filling ability of the silicon oxide layer
206
, which may further cause a void
208
, or voids, to form in the silicon oxide
206
.
SUMMARY OF THE INVENTION
The present invention provides a method of fabricating a shallow trench isolation to prevent formations of clipped corners, voids, and damage regions.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of fabricating a shallow trench isolation. A pad oxide layer and a mask layer are formed on a substrate. The pad oxide layer, and the mask layer are patterned to form a trench in the substrate. A first high-density plasma chemical vapor deposition is performed without providing argon gas. A conformal liner oxide layer is formed on the trench. A second high-density plasma chemical vapor deposition is performed with argon gas. A silicon oxide layer is formed on the liner oxide layer to fill the trench. A portion of the liner-oxide layer and the silicon oxide layer are removed to form a shallow trench isolation.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5726090 (1998-03-01), Jang et al.
patent: 5872058 (1999-02-01), Van Cleemput et al.
Chaudhuri Olik
Duy Mai Anh
Huang Jiawei
J C Patents
United Semiconductor Corp.
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