Method of fabricating shallow trench isolation

Details Method of fabricating shallow trench isolation Method of fabricating shallow trench isolation

1999-02-05

2001-06-19

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

C438S424000

Reexamination Certificate

active

06248641

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention The present invention relates to a method of fabricating shallow trench isolation, and more particularly to a process for fabricating shallow trench isolation to solve the issue of kink effect.
(2) Description of the Related Art
In recent years, the sizes of the MOSFETs and capacitors have become continuously smaller so that the packing densities of these ICs have increased considerably. It is necessary to isolate all of the transistors in order to prevent the transistors from affecting one another. At the early stage, the method of Local Oxidation (LOCOS) was used as the isolation process. The method of LOCOS uses thermal oxidation to form a field oxide layer to isolate all of the transistors. To use LOCOS as isolation process has a serious drawback—bird's beak. The bird's beak, the lateral extension of field oxide during thermal oxidation process, will affect the subsequent process at the active regions. This issue is getting serious in the field of sub-micron and deep sub-micron technology. Therefore, a lot of new isolation processes were developed to substitute the method of LOCOS.
Shallow trench isolation is the first candidate to substitute LOCOS. A typical structure would be formed in the following manner: Referring now more particularly to
FIG. 1A
, a pad oxide layer
13
and a nitride layer
15
are sequentially formed on a silicon substrate
11
. The pad oxide layer
13
and the nitride layer
15
are then patterned by the conventional photolithography and plasma etching techniques to define a shallow trench region
12
which separates active regions
14
.
Next, a second oxide layer
17
is deposited to fill the shallow trenches as shown in FIG.
1
A. An etching back step for removing part of the second oxide layer
17
is performed by chemical mechanical polishing (CMP) technique to provide a planarized surface. The CMP technique offers an advantage of whole wafer planarization without additional masking or coating steps. However, one of the difficulties encountered with CMP for trench planarization is “scratch” that occurs on the surface of the second oxide layer
17
. When the second oxide layer
17
and the nitride layer
15
are polished simultaneously, “scratch” is formed because of the hardness of the nitride layer. Another difficulty encountered with CMP for trench planarization is the “kink effect”. When the wet etching techniques are used to remove the nitride layer
15
, the isotropic etching will form a recess
19
on the edge between the active region
14
and the shallow trench
12
, as shown in FIG.
1
B. As a result the recess
19
will form an oxide-recess
19
a
on the edge of the two sides of the shallow trench during oxidizing and etching process. Transistors built on such silicon substrates will have problems of abnormal turn-on or early turn-on due to the scratch and the kink effect.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide a method of fabricating shallow trench isolation for high density integrated-circuit applications.
It is another object of the present invention to provide a method of fabricating shallow trench isolation by using a polysilicon layer as a stop layer to avoid the problem of “scratch” on a dielectric layer.
It is a further object of the present invention to provide a method of fabricating shallow trench isolation by using an oxide spacer to eliminate the kink effect.
These objects are accomplished by the fabrication process described below. Firstly, a pad oxide layer and a polysilicon layer are formed on a silicon substrate. The pad oxide layer and the polysilicon layer are etched to expose parts of the substrate. Then the exposed parts of the substrate are oxidized to form an oxide layer. Next, the oxide layer is etched back to form an oxide spacer on the side wall of the polysilicon. Then, shallow trench is formed by etching the partly exposed substrate. Next, a dielectric layer is formed to fill the shallow trench and etched back by CMP to stop on the polysilicon layer. Finally, the pad oxide layer and the polysilicon layer are removed. As a result, oxide spacers on the side wall of the shallow trench are formed to eliminate the kink-effect.


REFERENCES:
patent: 5899719 (1999-05-01), Hong
patent: 5981353 (1999-11-01), Tsai
patent: 6001706 (1999-12-01), Tan et al.

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