Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – On insulating substrate or layer
Reexamination Certificate
1999-01-20
2001-07-10
Niebling, John F. (Department: 2814)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
On insulating substrate or layer
C438S155000, C438S161000
Reexamination Certificate
active
06258684
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device, more particularly to a memory device having bipolar junction transistors on a SOI substrate, and a method of fabricating such a device.
BACKGROUND OF THE INVENTION
A conventional DRAM memory cell structure includes only a single MOS transistor and associated capacitor forming, as is well known, a diffused twin cell in a semiconductor substrate. In this case, when the conventional DRAM memory cell is formed on the SOI(silicon on insulator) substrate, unwanted charges are accumulated in the bulk substrate, thus altering the electrical properties of the bulk substrate. As a result, a floating body phenomenon, which changes the threshold voltage, occurs and the unit cell does not operate uniformly.
SUMMARY OF THE INVENTION
The present invention is intended to solve the above problems, and it is an object of the invention to provide a semiconductor memory device which prevents the floating body phenomenon and a method of forming such a device.
It is yet another object of the invention to provide a method to improve a degree of integration and operation characteristics of a semiconductor memory device.
Other aspects, objects, and the several advantages of the present invention will become apparent to one skilled in the art from a reading of the following disclosure and appended claims.
The above and other objects in accordance with the present invention may be realized by defining an active and an inactive region on a semiconductor layer of a SOI substrate, the semiconductor layer having a first type of conductivity, said inactive region serving as a device isolation region, and forming first and second impurity regions in the semiconductor layer by implanting second-type impurity ions into the active region, the first and second impurity regions having a second type of conductivity. The first and second impurity region are spaced from each other, and the active region between the first and second impurity regions serves as a base region. A base electrode is electrically connected to the base region, a bit line electrode is electrically connected to the first impurity region and a capacitor is electrically connected to the second impurity region. The base electrode may be constructed by forming a first interlayer insulating film over the semiconductor layer, forming a first contact hole by etching the first interlayer insulating film to expose portions of the base region, and filling the first contact hole with an electrically conductive material. The bit line electrode may be electrically connected to the first impurity region by forming a second interlayer insulating film over the first interlayer insulating film including the base electrode, forming a second contact hole by etching the first and second interlayer insulating films to expose portions ofthe first impurity region, filling the second contact hole with a first contact plug, and electrically connecting the bit line electrode to the first contact plug. The capacitor may be electrically connected to the second impurity region by forming a third interlayer insulating film over the second interlayer insulating film including the bit line electrode, forming a third contact hole by etching the first, second, and third interlayer insulating films to expose portions of the second impurity region, filling the third contact hole with a second contact plug and electrically connecting the capacitor to the second contact plug.
The above and other objects of the present invention may be also realized by a semiconductor layer of a SOI substrate, the semiconductor layer having first type of conductivity, a first impurity region made of portions of the semiconductor layer, and second and third impurity regions formed in the semiconductor layer, both outside of the first impurity region, the second and third impurity regions having second type of conductivity. A base electrode is electrically connected to the first impurity region, a bit line electrode is electrically connected to the second impurity region and a capacitor is electrically connected to the third impurity region. The base electrode may be formed by etching a first contact hole through a first interlayer insulating film formed over the semiconductor layer and filling the first contact hole with an electrically conductive material. The bit line electrode may be electrically connected to the second impurity region by forming a second interlayer insulating film formed over the first interlayer insulating film including the base electrode, etching through the first and second interlayer insulating films to form a second contact hole, filling the second contact hole with a first contact plug, and forming the bit line electrode. The capacitor may be electrically connected to the third impurity region by forming a third interlayer insulating film over the second interlayer insulating film including the bit line electrode, etching through the first, second and third interlayer insulating films to form a third contact hole, filling the third contact hole with a second contact plug, and electrically connecting the capacitor electrode to the second contact plug.
According to the present invention, the DRAM cell is fabricated by forming a bipolar transistor instead of the MOS transistor on the SOI substrate, thereby preventing the floating body phenomenon, thereby allowing the unit cell can operate uniformly.
REFERENCES:
patent: 5344785 (1994-09-01), Jermoe et al.
patent: 5763931 (1998-06-01), Sugiyama
patent: 5838043 (1998-11-01), Yuan
patent: 5946582 (1999-08-01), Bhat
Jones Volentine PLLC
Niebling John F.
Samsung Electronics Co,. Ltd.
Simkovic Viktor
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