Semiconductor device manufacturing: process – Making passive device – Planar capacitor
Reexamination Certificate
2000-01-06
2002-04-02
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making passive device
Planar capacitor
C438S386000, C438S396000, C438S253000, C438S240000
Reexamination Certificate
active
06365486
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to methods for manufacturing semiconductor devices. More particularly, the present invention relates to methods for fabricating a semiconductor device, such as a capacitor, which utilize in situ passivation of dielectric thin films during fabrication.
2. The Relevant Technology
As integrated circuit technology has progressed, it has become possible to store ever-increasing amounts of digital data in a smaller space at less expense and still access the data randomly, quickly and reliably. Central to this increased ability to store and retrieve data has been the dynamic random access memory (DRAM), fabricated as an integrated circuit. The memory cells of DRAMs are comprised of two main components, a transistor and a capacitor. The capacitor of each memory cell functions to store an electrical charge representing a digital value (e.g., a charged capacitor representing a
1
and a discharged capacitor representing a
0
) with the transistor acting as a switch to connect the capacitor to the “outside world” via decoding and other circuitry. In order to function properly, the capacitor must possess a minimum amount of capacitance. If a capacitor exhibits too little capacitance, it will cause errors in data storage.
The capacitive value of a capacitor is dependent upon the dielectric constant of the material placed between the plates of the capacitor, the distance btween the plates, and the effective area of the plates. In the case of integrated circuits, the material used as a dielectric between the plates is generally limited to only a few materials.
The interaction of dielectric materials and capacitor electrode materials plays a critical role in determining electrical properties such as leakage current of capacitors in integrated circuits and advanced packages. The electrode material can interact with the dielectric material during deposition and further processing. For example, the electrode material can adsorb some of the oxygen from the dielectric film, making the dielectric film oxygen deficient. The oxygen deficient dielectric film demonstrates current leakage, and is unacceptable for use in a DRAM or other semiconductor applications.
Various approaches have been developed in an attempt to reduce leakage current problems in capacitors. For example, U.S. Pat. No. 5,641,702 to Imai et al. discloses a method of forming an integrated circuit capacitor with an insulating film having a high permittivity, which includes annealing the insulating film in a reactive oxygen atmosphere to reduce leakage current in the capacitor. In U.S. Pat. No. 5,189,503 to Suguro et al., a capacitor having a two-part dielectric insulating layer is disclosed, including a first metal oxide film with pieces of a dissimilar metal element added to the oxide, such as tantalum oxide with a zirconium additive, and a second metal oxide film such as tungsten oxide. The disclosure in the Suguro patent indicates that excessive oxygen may be added to a tantalum oxide layer to reduce oxygen deficiency and the associated leakage current. In U.S. Pat. No. 5,153,685 to Murata et al., an integrated circuit capacitor having a two-part dielectric layer including silicon nitride and silicon dioxide is disclosed. The silicon nitride is formed on the lower electrode, and the silicon dioxide is formed from the silicon nitride by a high pressure oxidation process.
While the above approaches have made some progress in reducing leakage current problems in capacitors, there is still a need for improved capacitor fabrication methods that further reduce or prevent the adsorption of oxygen from dielectric films by capacitor electrodes.
SUMMARY OF THE INVENTION
The present invention is directed to methods of fabrication for semiconductor devices such as capacitors and novel capacitor structures formed thereby which can be used in memory cells of a DRAM device. The present methods provide a protective barrier in the form of one or more passivation layers in a capacitor structure, which reduce the interaction of an electrode and dielectric film in the capacitor at their interface. This reduces the diffusion of oxygen from the dielectric film to the electrode, thereby reducing current leakage and the like.
In one aspect of the present invention, various methods are provided for fabricating capacitor structures. In one method of the present invention, a first conductive layer or electrode is formed on a semiconductor substrate, and a dielectric layer is formed on the first conductive layer. The dielectric layer is exposed to or annealed in a reactive environment in order to form a passivation layer on the dielectric layer. The reactive environment that is used in forming the passivation layer is a gas or mixture of gases, which can optionally be altered using any type of plasma or energy. The dielectric layer can be optionally annealed in an oxidizing environment prior to forming the passivation layer thereover. A second conductive layer is then formed on the passivation layer to complete construction of the capacitor structure.
In an alternative method of the invention, the above steps are performed, except that the passivation layer and dielectric layer are annealed in an oxidative environment to saturate the passivation layer and the dielectric layer with oxygen prior to forming the second conductive layer. In a further alternative method, the steps of annealing in the reactive environment and annealing in the oxidative environment are repeated in a cyclic process prior to forming the second conductive layer.
In another method of the invention, a first conductive layer is formed on a semiconductor substrate, and the first conductive layer is exposed to a reactive environment in order to form a passivation layer on the first conductive layer. A dielectric layer is then formed on the passivation layer, and a second conductive layer is formed on the dielectric layer to complete construction of the capacitor structure. Alternatively, a second passivation layer can be formed on the dielectric layer prior to forming the second conductive layer.
In a further method of the invention, a first conductive layer is formed on a semiconductor substrate, and a thin first dielectric layer is formed on the first conductive layer. The first dielectric layer is then exposed to a reactive environment in order to form a passivation layer on the first dielectric layer. A second dielectric layer is then formed on the passivation layer, and a second conductive layer is formed on the second dielectric layer to complete construction of the capacitor structure. Alternatively, a second passivation layer can be formed on the second dielectric layer prior to forming the second conductive layer.
In another aspect of the invention, various capacitor structure embodiments fabricated according to the above described methods are provided.
Other aspects and features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.
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Stanley Wolf and Richard N. Tauber, “Silicon Processing for the VLSI Era, vol. 1: Process Technology,” Lattice
Agarwal Vishnu K.
Derderian Garo J.
Sandhu Gurtej S.
Bowers Charles
Micro)n Technology, Inc.
Smoot Stephen W.
Workman & Nydegger & Seeley
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