Method of fabricating semiconductor device including step of for

Details Method of fabricating semiconductor device including step of for Method of fabricating semiconductor device including step of for

1995-05-12

1997-05-06

Bowers, Jr., Charles L.

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

356401, 438975, H01L 2166

Patent

active

056270836

ABSTRACT:
A method of fabricating a semiconductor device includes the steps of forming an inner circuit, a cell test pattern, and a superposition error measurement pattern. The inner circuit includes a plurality of recurring basic cells. The cell test pattern includes a test cell array having at least one test basic cell of the same design as the basic cells in the inner circuit and a plurality of test dummy cells disposed around the test cell array. The superposition error measurement pattern includes a first and a second pattern formed in the steps of a first and a second lithographic step, respectively, performed in the formation of the basic cells. The inner circuit, said cell test pattern and said superposition error measure pattern are integrated on the same semiconductor substrate. The method permits the formation of the test basic cell having the same proximity effect as that of the basic cells and further permits accurate monitoring of the correlation of the extent of superposition of semiconductor circuit patterns and superposition error.

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Translation of JP 62-97327 (Wakamiya).
Translation of JP 55-113331 (Sakashita).

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