Method of fabricating semiconductor device including gold interc

Details Method of fabricating semiconductor device including gold interc Method of fabricating semiconductor device including gold interc

1997-06-11

1998-04-07

Quach, T. N.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438678, 438686, 438927, H01L 21288

Patent

active

057364605

ABSTRACT:
In a semiconductor device having gold interconnections for connecting elements formed on a substrate with each other, the improvement is that the average dimension of gold grains constituting the gold interconnections is determined to be 0.17 through 0.25 times as large as width of the gold interconnections. In addition, the average dimension of the gold grains is determined so that the mean time to failure is not less than a predetermined period of time.

REFERENCES:
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patent: 4674176 (1987-06-01), Tuckerman
patent: 5247204 (1993-09-01), Yokoyama
patent: 5272111 (1993-12-01), Kosaki
patent: 5475265 (1995-12-01), Kato
patent: 5502005 (1996-03-01), Mikagi
Fu, K., et al., "An Analytical Model for Linewidth-Dependent Electromigration Lifetime in VLSI Interconnects," Jun. 1990.
Symposium on VLSI Technology, IEEE, 4-7 Jun. 1990, pp. 29-30.

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