Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2002-06-17
2003-05-06
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
Reexamination Certificate
active
06559029
ABSTRACT:
RELATED APPLICATION
This application relies for priority upon Korean Patent Application No. 2001-34735, filed on Jun. 19, 2001, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a semiconductor device having a trench isolation structure.
BACKGROUND OF THE INVENTION
As semiconductor devices become highly integrated, widths of isolation layers become decreased for electrically isolating devices. Especially, in case of a trench isolation technique which has solved several problems of a LOCOS isolation technique, as semiconductor devices become highly integrated, an aspect ratio of a trench which is formed at a semiconductor substrate is increased, thereby creating a problem whereby it is difficult to fill the trench.
FIGS. 1 through 4
are cross-sectional views for explaining a conventional method of fabricating a trench isolation structure.
Referring to
FIG. 1
, a hard mask pattern
102
a
is formed to define a first isolation region
104
at a cell array region ‘a’ and a second isolation region
105
at a peripheral region ‘b’. In order to form the hard mask pattern
102
a,
a buffer oxide layer
101
and a hard mask layer are formed on the semiconductor substrate and sequentially patterned.
Referring to
FIG. 2
, the semiconductor substrate
100
is etched using the hard mask pattern
102
a
as an etch mask, to form trench regions T
1
at the cell array region ‘a’ and the peripheral circuit region ‘b’. Thus, the trench regions T
1
for forming a conventional trench isolation layer have the same depth regardless of the cell array region ‘a’ of a high pattern density and the peripheral circuit regions ‘b’ of a low pattern density.
Referring to
FIG. 3
, an insulation layer
107
is formed over the entire surface of the resultant structure where the trench region T
1
is formed, to fill the trench region. As seen in
FIG. 2
, in the conventional method of fabricating the trench isolation, trench regions T
1
of the same depth are formed regardless of the pattern density. Thus, as semiconductor devices become more highly integrated, when the insulation layer
107
is formed to fill the trench region T
1
, a void B can be generated at the cell array region ‘a’ of the high pattern density. By using a material layer having a superior burial characteristic, for example, a O
3
-TEOS oxide layer or a high density plasma (HDP) CVD layer, as an insulation layer for filling the trench region T
1
, it is possible to increase the burial characteristic of the insulation layer. But, in the conventional method, despite using the material layer having a superior burial characteristic, if the aspect ratio of the trench region is high, there remains a high probability that the void B′ occurs.
Referring to
FIG. 4
, the insulation layer
107
is etched by using a chemical mechanical polishing (CMP) process to expose the top of the hard mask pattern
102
a.
And, the hard mask pattern
102
a
and the buffer oxide layer
101
are removed to form isolation layers
107
a
and
107
b
filling the trench region T
1
, and at the same time, to expose active regions between the isolation layers
107
a
and
107
b.
At this time, at the step of forming the insulation layer
107
, the void B of the cell array region ‘a’ is exposed, so that a groove B′ is formed at the top of the isolation layer
107
a
of the cell array region of the high pattern density and this produces an undesirable effect on the characteristic of a semiconductor device.
As described above, the conventional method of fabricating trench isolation simultaneously forms trench regions at a cell array region of a high pattern density and at a peripheral circuit region of a low pattern density. Thus, for a device isolation of a peripheral circuit where high voltage is applied, a trench region should be formed deeply, and thus, a void can be generated at a cell array region of high pattern density. Thus, it is required to form a shallow trench at the cell array region of the high pattern density and a relatively deep trench region at the peripheral circuit region.
The Korean laid-open patent number 1999-0042687 provides a method of fabricating trench regions having each different depth at a cell array region and a peripheral circuit region. But, the method includes twice as many photolithography processes for forming the trench regions at the cell array region and the peripheral circuit region. Thus, the process is complicated and has a problem of degrading a characteristic of the interface between an isolation layer and a semiconductor substrate, since a first formed trench region, out of trench regions formed at a cell array region and at a peripheral circuit region, is covered by a photoresist.
SUMMARY OF THE INVENTION
Thus, it is an object of the present invention to provide a method of fabricating a semiconductor device which has trench isolation structures of different thicknesses at a cell array region of a high pattern density, and at a peripheral circuit region of a low pattern density without addition of a photolithography process.
In order to approach the object, the present invention provides a method including the following steps. A hard mask layer is formed on a semiconductor substrate having a cell array region and a peripheral circuit region. The hard mask layer is patterned to expose the semiconductor substrate. Thus, a hard mask pattern is formed to define a first isolation region at the cell array region and a second isolation region at the peripheral circuit region. A sacrificial material layer is formed at the entire surface of the resultant structure where the hard mask pattern is formed. The sacrificial material layer is conformally formed over the entire surface of the second isolation region and the hard mask pattern of the peripheral circuit region, and fills a gap region between the hard mask patterns of the cell array region. The sacrificial material layer and the semiconductor substrate are sequentially etched to form a first and a second trench regions at the cell array region and the peripheral circuit region, respectively. The first trench region is shallower than the second trench region.
Further, after forming an insulation layer filling the first and second trench regions, the insulation layer is etched by using a CMP process to expose the hard mask layer and simultaneously to form an isolation layer at the first and second trench regions. Then, the hard mask layer is removed to expose the semiconductor substrate between the isolation layers.
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patent: 5385861 (1995-01-01), Bashir et al.
patent: 5504033 (1996-04-01), Bajor et al.
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patent: 5691232 (1997-11-01), Bashir et al.
patent: 5817568 (1998-10-01), Chao
patent: 5893744 (1999-04-01), Wang
patent: 5950093 (1999-09-01), Wei
patent: 6207534 (2001-03-01), Chan et al.
patent: 6406976 (2002-06-01), Singh et al.
patent: 10-12716 (1998-10-01), None
patent: 1999-0042687 (1999-06-01), None
English language abstract of Korean Publication No. 1999-0042687.
Blum David S
Jr. Carl Whitehead
Marger & Johnson & McCollom, P.C.
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